Abstract: A strigolactone analog-based composition comprising at least one compound represented by: (I) wherein Ra, Rb, Rc, Rf, Re, and Rz are selected. The compositions can be used in, for example, plant growth regulation and weed control, including controlling the germination of parasitic root plants, inhibiting rice tillering, and triggering leaf senescence.

Abstract: Provided is a readily adhesive polyester film that has antistatic properties-and prevents an antistatic agent from transferring to other items The readily adhesive polyester film includes a polyester film and a readily adhesive layer on at least one surface of the polyester film, wherein the readily adhesive layer is formed of a cured composition containing an ion-conducting antistatic agent, a polyester resin, and a polycarbonate urethane resin, a surface of the readily adhesive layer has a surface specific resistance value of 1.0×1013 ?/sq or lower, and after the surface of the readily adhesive layer is brought into contact with an additional polyester film and maintained at a temperature of 50° C. under a pressure of 1 kg/cm2 for 3 days, the surface of the additional polyester film that is in contact with the surface of the readily adhesive layer has a surface specific resistance value of 1.0×1014 ?/sq or higher.

Abstract: A strigolactone analog-based composition comprising at least one compound represented by: (I) wherein Ra, Rb, Rc, Rf, Re, and Rz are selected. The compositions can be used in, for example, plant growth regulation and weed control, including controlling the germination of parasitic root plants, inhibiting rice tillering, and triggering leaf senescence.

Abstract: A readout circuit for reading out an output current from a photoelectric conversion element which collectively outputs currents generated in a plurality of pixels, each of which includes an avalanche photodiode, includes a current mirror circuit configured to receive the output current and output first and second currents having magnitudes in proportion to the output current, a photon counting circuit configured to count the number of photons incident on the photoelectric conversion element on the basis of the first current, an integral circuit configured to integrate the second current to generate a voltage signal, and a signal processing unit configured to determine a magnitude of light incident on the photoelectric conversion element on the basis of a counting result output from the photon counting circuit and a magnitude of the voltage signal output from the integral circuit.

Abstract: A readout circuit for reading out an output current from a photoelectric conversion element which collectively outputs currents generated in a plurality of pixels, each of which includes an avalanche photodiode, includes a current mirror circuit configured to receive the output current and output first and second currents having magnitudes in proportion to the output current, a photon counting circuit configured to count the number of photons incident on the photoelectric conversion element on the basis of the first current, an integral circuit configured to integrate the second current to generate a voltage signal, and a signal processing unit configured to determine a magnitude of light incident on the photoelectric conversion element on the basis of a counting result output from the photon counting circuit and a magnitude of the voltage signal output from the integral circuit.

Abstract: A polyurethane porous membrane is produced by a simple method to be used for at least one of applications of cell culture and cancer cell growth inhibition. The production method of the polyurethane porous membrane to be used for at least one of the applications of cell culture and cancer cell growth inhibition comprises: a first step of forming a layer of a polyurethane material which is uncured, on a substrate; and a second step of supplying water vapor to an exposed surface of the layer of the polyurethane material formed on the substrate, which is away from the substrate, so as to cure the polyurethane material and provide the layer of the polyurethane material with a porous structure having a plurality of irregularities on the exposed surface.

Abstract: A reverse bias voltage is applied to a photodiode array provided with a plurality of avalanche photodiodes operated in Geiger mode and with quenching resistors connected in series to the respective avalanche photodiodes. Electric current is measured with change of the reverse bias voltage applied, and the reverse bias voltage at an inflection point in change of electric current measured is determined as a reference voltage. A voltage obtained by adding a predetermined value to the determined reference voltage is determined as a recommended operating voltage.

Abstract: A polyurethane porous membrane is produced by a simple method to be used for at least one of applications of cell culture and cancer cell growth inhibition. The production method of the polyurethane porous membrane to be used for at least one of the applications of cell culture and cancer cell growth inhibition comprises: a first step of forming a layer of a polyurethane material which is uncured, on a substrate; and a second step of supplying water vapor to an exposed surface of the layer of the polyurethane material formed on the substrate, which is away from the substrate, so as to cure the polyurethane material and provide the layer of the polyurethane material with a porous structure having a plurality of irregularities on the exposed surface.

Abstract: According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface.

Abstract: A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.

Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.

Abstract: According to one embodiment, a semiconductor device includes: a substrate; a first conductive portion extending in a first direction perpendicular to a major surface of the substrate; a second conductive portion extending in the first direction; a semiconductor portion provided between the first and the second conductive portions and including a first semiconductor region; a first electrode portion extending in the first direction between the first and the second conductive portions; a second electrode portion extending in the first direction between the first and the second conductive portions; a first insulting portion provided between the first electrode portion and the semiconductor portion and having a first thickness; and a second insulating portion provided between the second electrode portion and the semiconductor portion and having a second thickness greater than the first thickness.

Abstract: A reverse bias voltage is applied to a photodiode array provided with a plurality of avalanche photodiodes operated in Geiger mode and with quenching resistors connected in series to the respective avalanche photodiodes. Electric current is measured with change of the reverse bias voltage applied, and the reverse bias voltage at an inflection point in change of electric current measured is determined as a reference voltage. A voltage obtained by adding a predetermined value to the determined reference voltage is determined as a recommended operating voltage.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface.

Abstract: A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

Abstract: According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second semiconductor region of the first conductivity type and a second electrode. The first semiconductor region includes a first portion including a first major surface and a second portion extending in a first direction perpendicular to the first major surface on the first major surface. The first electrode includes a third portion provided to face the second portion and is provided to be separated from the first semiconductor region. The second semiconductor region is provided between the second and third portions, includes a first concentration region having a lower impurity concentration than the first semiconductor region and forms a Schottky junction with the third portion. The second electrode is provided on an opposite side of the first major surface and in conduction with the first portion.

Abstract: There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the f