Patents by Inventor Tsuyoshi Ohta

Tsuyoshi Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7910440
    Abstract: A semiconductor device includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the gate oxide film. The semiconductor device also includes: a second trench that is formed in the semiconductor substrate with a width wider than the width of the first trench; and a terminal-embedded insulation layer that is formed so as to bury the second trench. The semiconductor device further includes: a third trench that is formed in the semiconductor substrate with a width wider than the width of the second trench; and a trench contact electrode that is formed so as to bury the third trench.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Ohta, Takahiro Kawano
  • Patent number: 7525133
    Abstract: A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: April 28, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Ohta, Bungo Tanaka
  • Publication number: 20090032875
    Abstract: There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the f
    Type: Application
    Filed: August 4, 2008
    Publication date: February 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke KAWAGUCHI, Kazuya Nakayama, Tsuyoshi Ohta, Takeshi Uchihara, Takahiro Kawano, Yuji Kato
  • Publication number: 20080164517
    Abstract: A semiconductor device according to the present invention includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the gate oxide film. The semiconductor device also includes: a second trench that is formed in the semiconductor substrate with a width wider than the width of the first trench; and a terminal-embedded insulation layer that is formed so as to bury the second trench. The semiconductor device further includes: a third trench that is formed in the semiconductor substrate with a width wider than the width of the second trench; and a trench contact electrode that is formed so as to bury the third trench.
    Type: Application
    Filed: January 2, 2008
    Publication date: July 10, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi OHTA, Takahiro Kawano
  • Publication number: 20070145416
    Abstract: A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.
    Type: Application
    Filed: December 27, 2006
    Publication date: June 28, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi Ohta, Bungo Tanaka
  • Patent number: 6200156
    Abstract: A lead wire connection terminal fitment capable of permitting a plurality of lead wires to be readily press-fitted in a single lead wire press fit groove. The terminal fitment may be in the form of a relay terminal fitment, which includes a metal plate formed with a lead wire press fit groove by machining in which lead wires are press-fitted. A pair of inner surfaces of the metal plate defining the lead wire press fit groove therebetween are formed thereon with a plurality of projections and recesses engaged with an outer periphery of lead wires. The projections biting into the lead wires are so arranged that a space defined between the projections opposite to each other is reduced in width at a position thereof spaced by a distance in a depth direction of the lead wire press fit groove, resulting in being divided into a first space portion increased in width and a second space portion decreased in width.
    Type: Grant
    Filed: November 26, 1999
    Date of Patent: March 13, 2001
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Kenichi Hiraki, Tsuyoshi Ohta, Kazufumi Daimon
  • Patent number: 5721526
    Abstract: A high-voltage variable resistor capable of significantly reducing a circuit board as compared with a prior art. Terminal fitments each are arranged so as to function as a connector for forming electrical connection between a slide element slid on each of variable resistance patterns and a terminal acting as an output section. A contact point between a contact on a contact support of the terminal fitment and a plate-like member of the slide element is positioned apart from a surface of the circuit board. The terminal fitment includes a positioner, which is positioned outside the pattern in a radial direction thereof, so that the positioner intersects the pattern while being spaced therefrom.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: February 24, 1998
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Kazufumi Daimon, Tsuyoshi Ohta, Kenichi Hiraki
  • Patent number: 5631087
    Abstract: An electrostatic image-bearing dielectric member comprises a support and a dielectric layer formed on the support. The dielectric layer is formed of at least one of amorphous carbon, diamond-like carbon and diamond. The dielectric layer may contain not larger than 60 atomic percent of at least one of hydrogen and fluorine. An intermediate layer may be provided between the support and the dielectric layer in order to improve the adhesion therebetween.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 20, 1997
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Yuzuru Fukuda, Shigeru Yagi, Tsuyoshi Ohta, Masato Ono
  • Patent number: 5592274
    Abstract: In an electrophotographic system, an electrostatic latent image as formed on a photoreceptor is developed with a developing agent to form a toner image thereon, a transfer paper is laid over the toner image and pressure is applied to the photoreceptor and the transfer paper so as to transfer or simultaneously transfer and fix the toner image onto the transfer paper. The photoreceptor is one having a surface protecting layer and a light-sensitive layer made of a hydrogenated and/or fluorinated amorphous silicon. The light-sensitive layer and the surface protecting layer of the photoreceptor are uniformly heated to a constant temperature. A charging device or a discharging brush or blade is used as a device of discharging the charges of the photoreceptor after the transference.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: January 7, 1997
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Taketoshi Higashi, Shigeru Yagi, Yuzuru Fukuda, Masato Ono, Masao Watanabe, Tsuyoshi Ohta
  • Patent number: 5578815
    Abstract: A bias circuit for applying a bias voltage to an avalanche photodiode APD2 for detecting light comprises a first diode APD1, a power supply V.sub.H connected to the first diode APD1, for applying a voltage to make the diode in breakdown between an anode and a cathode of the first diode APD1, and a constant voltage circuit V2 connected to the avalanche photodiode APD2 for detecting light, for applying a voltage difference of a breakdown voltage generated between the anode and the cathode of the first diode APD1 minus a constant voltage to the avalanche photodiode. The constant voltage is substantially independent from current flowing in the avalanche photodiode APD2 for detecting light to the avalanche photodiode.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: November 26, 1996
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Shigeki Nakase, Shigeyuki Nakamura, Tsuyoshi Ohta
  • Patent number: 5556729
    Abstract: An electrophotographic photoreceptor comprising: an electrically conductive substrate, a charge injection blocking layer formed on said electrically conductive substrate, a photoconductive layer comprising a single layer formed on said charge injection blocking layer, said photoconductive layer comprising amorphous silicon containing boron, a positive hole capturing layer formed on said photoconductive layer, said positive hole capturing layer being selected from the group comprising amorphous silicon containing less than 50 ppm boron and amorphous silicon being substantially composed of hydrogen and silicon atoms, and a surface layer formed on said positive hole capturing layer. The boron concentration contained in said photoconductive layer is 0.01-1000 ppm. The surface layer is formed by amorphous silicon nitride, amorphous silicon oxide, amorphous silicon carbide or amorphous carbon as a main body. The charge injection blocking layer has amorphous silicon as a main body and contains a group V element.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 17, 1996
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Yuzuru Fukuda, Tsuyoshi Ohta, Masato Ono, Taketoshi Higashi, Shigeru Yagi
  • Patent number: 5548112
    Abstract: A photodetecting circuit using an avalanche photodiode of the present invention has an avalanche photodiode, and a bias control means for applying a bias voltage to the avalanche photodiode to drive the avalanche photodiode at a high multiplication factor. The bias control means has a diode having the same temperature dependence of a breakdown voltage as that of the avalanche photodiode, and a control circuit for applying positive and negative potentials with respect to the ground potential between the anode and the cathode of the diode such that the diode is set in a breakdown state at a predetermined current. A positive or negative potential is applied from one of the anode and the cathode of the avalanche photodiode as a bias voltage, and a photocurrent is output from the other terminal of the avalanche photodiode.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: August 20, 1996
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Shigeki Nakase, Shigeyuki Nakamura, Tsuyoshi Ohta
  • Patent number: 5532669
    Abstract: A high-voltage variable resistor includes a terminal fitment having an increased number of edge elements while being simplified in structure and down-sized. A circuit substrate which includes a circuit pattern having a plurality of electrodes and resistor elements formed thereon is received in a substrate receiving section of an insulating casing. The insulating casing is charged with insulating resin through an opening thereof to form an insulating resin layer on a rear surface of the circuit substrate. Terminal fitments are provided each of which includes a core holding section provided with three or more edge elements biting into a periphery of a core of a lead wire inserted thereinto. The edge elements each are formed between each adjacent two of three or more slits formed at a plate-like section of the terminal fitment so as to radially extend from a center thereof.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: July 2, 1996
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Ichiro Tsunezawa, Hiromasa Saikatsu, Tsuyoshi Ohta
  • Patent number: 5514507
    Abstract: An electrophotographic photoreceptor for positive electrification comprising at least an electroconductive layer, a charge injection blocking layer, a photoconductive layer and a surface layer. The photoconductive layer comprises a layer having an amorphous silicon layer containing one or more of hydrogen, halogen and a Group III element for controlling electroconductivity and layer having an amorphous silicon germanium layer containing at least hydrogen, halogen and a Group III element. The charge injection blocking layer comprises an amorphous silicon layer containing hydrogen and a Group III element in an amount of equal or less than 1000 ppm. The electrophotographic photoreceptor has excellent electrification characteristics with dark and light sensitivities, stability against repetitive use and may be utilized as a photoreceptor for a semiconductor laser beam printer.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: May 7, 1996
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shigeru Yagi, Tsuyoshi Ohta
  • Patent number: 5494982
    Abstract: A process for the preparation of an ethylenic polymer composition having excellent physical properties such as high impact properties, environmental stress cracking resistance, pinch-off fusing characteristics and having an intrinsic viscosity ranging from 3.2 to 4.5 dl/g and a density ranging from 0.943 g/cm.sup.3 to 0.958 g/cm.sup.3.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: February 27, 1996
    Assignee: Idemitsu Petrochemical Company, Limited
    Inventors: Kenji Nakacho, Norio Shimakura, Tsutomu Akimaru, Tsuyoshi Ohta, Hideo Funabashi, Isamu Yamamoto
  • Patent number: 5462827
    Abstract: A negative-charging electrophotographic photoreceptor comprising an electrically conductive support having consecutively thereon (a) a charge injection prevention layer having a thickness of from 0.15 to 10 .mu.m, (b) a photoconductive layer, and (c) a surface layer, the charge injection prevention layer (a) comprising amorphous silicon containing at least one of a hydrogen atom and a halogen atom, and containing a nitrogen atom in an atomic ratio of from 0.01 to 0.65 to the silicon atom, the photoconductive layer (b) comprising amorphous silicon containing at least one of a hydrogen atom and a halogen atom.
    Type: Grant
    Filed: January 18, 1994
    Date of Patent: October 31, 1995
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shigeru Yagi, Masato Ono, Taketoshi Higashi, Tsuyoshi Ohta, Yuzuru Fukuda
  • Patent number: 5352555
    Abstract: An electorphotographic photoreceptor comprises an electroconductive support at least whose indentation hardness of surface is 100 and over on the Vickers hardness scale; a photoconductive layer comprising amorphous silicon containing at least one of hydrogen and halogen; and a surface layer comprising at least one of an amorphous silicon layer containing at least one of nitrogen, oxygen, and carbon, and an amorphous carbon layer containing at least one of not exceeding 50 atm. % of hydrogen and halogen. This photoreceptor is long-lived and causing no image defects that would otherwise develop in connection with the support, and it can be applied to an energy-saving, low-cost and highly reliable electrophotographic process and apparatus.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: October 4, 1994
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shigeru Yagi, Tsuyoshi Ohta, Taketoshi Higashi, Masao Watanabe, Kazuo Yano, Masato Ono, Yuzuru Fukuda
  • Patent number: D580818
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: November 18, 2008
    Inventors: Tsuyoshi Ohta, Rumi Ohta
  • Patent number: D589698
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: April 7, 2009
    Inventors: Tsuyoshi Ohta, Rumi Ohta
  • Patent number: D603601
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: November 10, 2009
    Inventors: Tsuyoshi Ohta, Rumi Ohta