Patents by Inventor Tsuyoshi Ohtsuki
Tsuyoshi Ohtsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11824070Abstract: The present invention is a silicon single crystal substrate for a solid-state image sensor obtained by slicing a silicon single crystal fabricated by a CZ method, where the silicon single crystal substrate is a p-type silicon single crystal substrate whose main dopant is Ga, and the silicon single crystal substrate has a B concentration of 5×1014 atoms/cm3 or less. This provides a silicon single crystal substrate and a silicon epitaxial wafer for a solid-state image sensor that can suppress the residual image characteristics of a solid-state image sensor.Type: GrantFiled: November 4, 2020Date of Patent: November 21, 2023Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Takao Abe, Tsuyoshi Ohtsuki
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Publication number: 20230276716Abstract: A method produces a semiconductor apparatus for a quantum computer. The apparatus includes: a semiconductor substrate; a quantum computer device formed on the semiconductor substrate; and a peripheral circuit formed on the semiconductor substrate and connected to the quantum computer device. The apparatus is to be used as a quantum computer. The method includes: a step of forming the quantum computer device and the peripheral circuit on the semiconductor substrate; and a step of deactivating a carrier in the semiconductor substrate by irradiation of a particle beam to at least a formation part for the quantum computer device and a formation part for the peripheral circuit in the semiconductor substrate. The method for producing a semiconductor apparatus for a quantum computer can produce a semiconductor apparatus for a quantum computer having excellent 3HD characteristics.Type: ApplicationFiled: May 26, 2021Publication date: August 31, 2023Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
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Publication number: 20230268175Abstract: The present invention is a method for forming a thermal oxide film on a semiconductor substrate, including: a correlation acquisition step of providing a plurality of semiconductor substrates each having a chemical oxide film having a different constitution formed by cleaning, performing a thermal oxidization treatment under identical thermal oxidization treatment conditions to form a thermal oxide film, and determining a correlation between the constitution of the chemical oxide film and a thickness of the thermal oxide film in advance; a cleaning condition determination step of determining the constitution of the chemical oxide film based on the correlation obtained in the correlation acquisition step so that a thickness of a thermal oxide film to be formed on a semiconductor substrate is a predetermined thickness, and determining cleaning conditions for forming a chemical oxide film having the determined constitution of the chemical oxide film; a substrate cleaning step of cleaning the semiconductor substrType: ApplicationFiled: March 10, 2021Publication date: August 24, 2023Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Tatsuo ABE
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Publication number: 20230230926Abstract: A method for producing a semiconductor apparatus capable of producing a semiconductor apparatus with improved transmission loss characteristic using an interposer substrate in which semiconductor devices formed on a silicon single crystal substrate are connected to each other by a through electrode, the method including: a step of providing the silicon single crystal substrate containing a dopant; a step of forming the semiconductor devices and the through electrode on the silicon single crystal substrate to obtain the interposer substrate; and a step of irradiating a particle beam to at least around a formation part for the through electrode on the silicon single crystal substrate to deactivate the dopant in a region around the formation part for the through electrode.Type: ApplicationFiled: May 26, 2021Publication date: July 20, 2023Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
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Publication number: 20230207399Abstract: A method for dry-etching a semiconductor substrate having an oxide film, including: evaluating a film quality of the oxide film and determining a time for performing the dry-etching on a basis of results of the evaluation in advance. This provides a method for controlling the etching amount of an oxide film accurately and suppressing over-etching and insufficient etching without influence from variation in the film quality of the oxide film when dry-etching the oxide film on the surface of the semiconductor substrate.Type: ApplicationFiled: March 3, 2021Publication date: June 29, 2023Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Tatsuo ABE
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Publication number: 20230170208Abstract: A method for forming a thermal oxide film on a semiconductor substrate, including: a correlation acquisition step of providing a plurality of semiconductor substrates; a substrate cleaning step of cleaning a semiconductor substrate; a thermal oxide film thickness estimation step of determining a constitution of a chemical oxide film formed on the semiconductor substrate by the cleaning in the substrate cleaning step and, based on the correlation, estimating a thickness of a thermal oxide film on a hypothesis that the semiconductor substrate has been subjected to a thermal oxidization treatment conditions in the correlation acquisition step; a thermal oxidization treatment condition determination step of determining thermal oxidization treatment conditions based on the thermal oxidization treatment conditions in the correlation acquisition step so that the thermal oxide film is a predetermined thickness; and a thermal oxide film formation step of forming a thermal oxide film on the semiconductor substrate.Type: ApplicationFiled: March 8, 2021Publication date: June 1, 2023Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Tatsuo ABE
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Publication number: 20220285228Abstract: A method for evaluating electrical characteristics of a semiconductor substrate, the method including the steps of: forming a p-n junction on a surface of the semiconductor substrate; mounting the semiconductor substrate on a wafer chuck provided with an equipment for performing light irradiation on the surface of the semiconductor substrate and an equipment for measuring the quantity of the light for the irradiation; performing light irradiation on the surface of the semiconductor substrate for a predetermined time; and measuring an amount of carriers generated after the light irradiation of the p-n junction at least after turning off the light irradiation. This provides a method for evaluating a semiconductor substrate that allows the same evaluation in a wafer state as when an actual solid-state image sensor has been formed without producing a device by using process equipment when evaluating characteristics corresponding to residual image characteristics of a wafer.Type: ApplicationFiled: June 4, 2020Publication date: September 8, 2022Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventor: Tsuyoshi OHTSUKI
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Patent number: 11248306Abstract: An anodic-oxidation equipment for forming a porous layer on a substrate to be treated, including: an electrolytic bath filled with an electrolytic solution; an anode and a cathode disposed in the electrolytic solution; and a power supply for applying current between the anode and the cathode in the electrolytic solution, wherein the anode is the substrate to be treated, and the cathode is a silicon substrate having a surface on which a nitride film is formed. This provides a cathode material in anodic-oxidation for forming porous silicon by an electrochemical reaction in an HF solution, the cathode material having a resistance to electrochemical reaction in an HF solution and no metallic contamination, etc., and furthermore, being less expensive than a conventional cathode material. Furthermore, high-quality porous silicon is provided at a lower cost than has been conventional.Type: GrantFiled: April 2, 2019Date of Patent: February 15, 2022Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi Ohtsuki, Masaro Tamatsuka
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Publication number: 20210238762Abstract: An anodic-oxidation equipment for forming a porous layer on a substrate to be treated, including: an electrolytic bath filled with an electrolytic solution; an anode and a cathode disposed in the electrolytic solution; and a power supply for applying current between the anode and the cathode in the electrolytic solution, wherein the anode is the substrate to be treated, and the cathode is a silicon substrate having a surface on which a nitride film is formed. This provides a cathode material in anodic-oxidation for forming porous silicon by an electrochemical reaction in an HF solution, the cathode material having a resistance to electrochemical reaction in an HF solution and no metallic contamination, etc., and furthermore, being less expensive than a conventional cathode material. Furthermore, high-quality porous silicon is provided at a lower cost than has been conventional.Type: ApplicationFiled: April 2, 2019Publication date: August 5, 2021Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Masaro TAMATSUKA
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Publication number: 20210159259Abstract: The present invention is a silicon single crystal substrate for a solid-state image sensor obtained by slicing a silicon single crystal fabricated by a CZ method, where the silicon single crystal substrate is a p-type silicon single crystal substrate whose main dopant is Ga, and the silicon single crystal substrate has a B concentration of 5×1014 atoms/cm3 or less. This provides a silicon single crystal substrate and a silicon epitaxial wafer for a solid-state image sensor that can suppress the residual image characteristics of a solid-state image sensor.Type: ApplicationFiled: November 4, 2020Publication date: May 27, 2021Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Takao ABE, Tsuyoshi OHTSUKI
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Patent number: 10886129Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.Type: GrantFiled: July 3, 2017Date of Patent: January 5, 2021Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi Ohtsuki, Tadashi Nakasugi, Hiroshi Takeno, Katsuyoshi Suzuki
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Publication number: 20190267239Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.Type: ApplicationFiled: July 3, 2017Publication date: August 29, 2019Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Tadashi NAKASUGI, Hiroshi TAKENO, Katsuyoshi SUZUKI
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Patent number: 9935021Abstract: A method for evaluating a semiconductor wafer including preparing a reference wafer in which contamination element and amount of contamination are known, forming a plurality of cells including p-n junctions on the reference wafer, measuring junction leakage currents in the plurality of cells on the reference wafer to acquire a distribution of the junction leakage currents of the reference wafer, associating the distribution of the junction leakage currents of the reference wafer with a contamination element, forming a plurality of cells including p-n junctions on a wafer to be measured, measuring junction leakage currents in the plurality of cells on the wafer to be measured to acquire a distribution of the junction leakage currents of the wafer to be measured, and identifying a contamination element of the wafer to be measured based on the association.Type: GrantFiled: April 14, 2014Date of Patent: April 3, 2018Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventor: Tsuyoshi Ohtsuki
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Patent number: 9780006Abstract: An SOI substrate evaluating method includes: forming a device onto a measuring SOI substrate, and previously determining a relationship between an interface state density and a leakage power upon application of radio-frequency thereon, or converting the interface state density to a resistance followed by previously determining a relationship between the converted resistance and the leakage power; measuring an interface state density of the evaluation target SOI substrate to determine the interface state density or a resistance converted from the interface state density; evaluating a leakage power of the evaluation target SOI substrate from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the interface state density and the leakage power, or from a resistance converted from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the resistance and leakage power.Type: GrantFiled: February 25, 2015Date of Patent: October 3, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventor: Tsuyoshi Ohtsuki
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Patent number: 9748151Abstract: The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.Type: GrantFiled: February 23, 2015Date of Patent: August 29, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi Ohtsuki, Hiroshi Takeno
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Patent number: 9696368Abstract: On an EP substrate 1, an EP layer 2 having a conductivity type different from that of the EP substrate 1 is grown. With ion implantation, a well 5 having the same conductivity type as the EP layer 2 is formed, and a channel stop layer 10 is also formed. A dopant having a conductivity type different from that of the well 5 is diffused in the well 5 to form a pn junction 7 in the well 5. A plurality of cells 20 each having the diffusion layer 6 as one electrode and a rear surface 1a as the other electrode are formed as a TEG. Using the TEG, junction leakage currents from two depletion layers, a depletion layer 8 in the well and a depletion layer 4 at an interface between the EP layer 2 and the EP substrate 1, are measured.Type: GrantFiled: April 25, 2013Date of Patent: July 4, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventor: Tsuyoshi Ohtsuki
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Publication number: 20170047258Abstract: An SOI substrate evaluating method includes: forming a device onto a measuring SOI substrate, and previously determining a relationship between an interface state density and a leakage power upon application of radio-frequency thereon, or converting the interface state density to a resistance followed by previously determining a relationship between the converted resistance and the leakage power; measuring an interface state density of the evaluation target SOI substrate to determine the interface state density or a resistance converted from the interface state density; evaluating a leakage power of the evaluation target SOI substrate from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the interface state density and the leakage power, or from a resistance converted from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the resistance and leakage power.Type: ApplicationFiled: February 25, 2015Publication date: February 16, 2017Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventor: Tsuyoshi Ohtsuki
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Publication number: 20160365293Abstract: The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.Type: ApplicationFiled: February 23, 2015Publication date: December 15, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
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Publication number: 20160351415Abstract: A semiconductor substrate for flash lamp anneal is used in a manufacturing process of performing ion implantation to form a p-n junction on a semiconductor substrate surface and recovering an ion implantation defect by the flash lamp anneal, carbon concentration of the semiconductor substrate being 0.5 ppma or less. Consequently, it is possible to provide the semiconductor substrate for flash lamp anneal which can easily and surely prevent the ion implantation defect from remaining in a device using a flash lamp anneal process.Type: ApplicationFiled: January 26, 2015Publication date: December 1, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
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Publication number: 20160079130Abstract: A method for evaluating a semiconductor wafer including preparing a reference wafer in which contamination element and amount of contamination are known, forming a plurality of cells including p-n junctions on the reference wafer, measuring junction leakage currents in the plurality of cells on the reference wafer to acquire a distribution of the junction leakage currents of the reference wafer, associating the distribution of the junction leakage currents of the reference wafer with a contamination element, forming a plurality of cells including p-n junctions on a wafer to be measured, measuring junction leakage currents in the plurality of cells on the wafer to be measured to acquire a distribution of the junction leakage currents of the wafer to be measured, and identifying a contamination element of the wafer to be measured based on the association.Type: ApplicationFiled: April 14, 2014Publication date: March 17, 2016Inventor: Tsuyoshi OHTSUKI