Patents by Inventor Tsuyoshi Ohtsuki

Tsuyoshi Ohtsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160079130
    Abstract: A method for evaluating a semiconductor wafer including preparing a reference wafer in which contamination element and amount of contamination are known, forming a plurality of cells including p-n junctions on the reference wafer, measuring junction leakage currents in the plurality of cells on the reference wafer to acquire a distribution of the junction leakage currents of the reference wafer, associating the distribution of the junction leakage currents of the reference wafer with a contamination element, forming a plurality of cells including p-n junctions on a wafer to be measured, measuring junction leakage currents in the plurality of cells on the wafer to be measured to acquire a distribution of the junction leakage currents of the wafer to be measured, and identifying a contamination element of the wafer to be measured based on the association.
    Type: Application
    Filed: April 14, 2014
    Publication date: March 17, 2016
    Inventor: Tsuyoshi OHTSUKI
  • Publication number: 20150145551
    Abstract: On an EP substrate 1, an EP layer 2 having a conductivity type different from that of the EP substrate 1 is grown. With ion implantation, a well 5 having the same conductivity type as the EP layer 2 is formed, and a channel stop layer 10 is also formed. A dopant having a conductivity type different from that of the well 5 is diffused in the well 5 to form a pn junction 7 in the well 5. A plurality of cells 20 each having the diffusion layer 6 as one electrode and a rear surface 1a as the other electrode are formed as a TEG. Using the TEG, junction leakage currents from two depletion layers, a depletion layer 8 in the well and a depletion layer 4 at an interface between the EP layer 2 and the EP substrate 1, are measured.
    Type: Application
    Filed: April 25, 2013
    Publication date: May 28, 2015
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventor: Tsuyoshi Ohtsuki
  • Patent number: 8900971
    Abstract: The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
  • Patent number: 8877609
    Abstract: A method for manufacturing a bonded substrate that has an insulator layer in part of the bonded substrate includes: partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; performing a heat treatment to the base substrate having the porous layer formed thereon to change the porous layer into the insulator layer, and thereby forming the insulator layer whose thickness partially varies on the bonding surface of the base substrate; removing the insulator layer whose thickness varies by an amount corresponding to a thickness of a small-thickness portion by etching; bonding the bonding surface of the base substrate on which an unetched remaining insulator layer is exposed to a bond substrate; and reducing a thickness of the bonded bond substrate and thereby forming a thin film layer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 4, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
  • Publication number: 20140120695
    Abstract: A method for manufacturing a bonded substrate that has an insulator layer in part of the bonded substrate includes: partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; performing a heat treatment to the base substrate having the porous layer formed thereon to change the porous layer into the insulator layer, and thereby forming the insulator layer whose thickness partially varies on the bonding surface of the base substrate; removing the insulator layer whose thickness varies by an amount corresponding to a thickness of a small-thickness portion by etching; bonding the bonding surface of the base substrate on which an unetched remaining insulator layer is exposed to a bond substrate; and reducing a thickness of the bonded bond substrate and thereby forming a thin film layer.
    Type: Application
    Filed: April 10, 2012
    Publication date: May 1, 2014
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yuuki Ooi, Wei Feng Qu, Tsuyoshi Ohtsuki, Kyoko Mitani, Fumio Tahara
  • Publication number: 20130341763
    Abstract: The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.
    Type: Application
    Filed: January 6, 2012
    Publication date: December 26, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yuuki Ooi, Wei Feng Qu, Tsuyoshi Ohtsuki, Kyoko Mitani, Fumio Tahara
  • Patent number: 8575722
    Abstract: A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: November 5, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Tsuyoshi Ohtsuki, Toru Takahashi, Wei Feig Qu
  • Patent number: 8551246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Publication number: 20110266655
    Abstract: A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.
    Type: Application
    Filed: December 8, 2009
    Publication date: November 3, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kiyoshi Mitani, Tsuyoshi Ohtsuki, Toru Takahashi, Wei Feig Qu
  • Patent number: 8043871
    Abstract: The present invention provides a method for forming an oxide film on a silicon wafer, comprising: measuring surface roughness of the silicon wafer and/or crystallinity in a surface layer portion of the silicon wafer in advance; adjusting oxidizing conditions for the silicon wafer based on the measurement value; and forming the oxide film on the silicon wafer under the adjusted oxidizing conditions. As a result, there can be provided the method for forming an oxide film by which the oxidizing conditions can be adjusted based on a state of the surface and/or the surface layer of the silicon wafer before forming the oxide film and even an ultrathin oxide film can be thereby accurately formed.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: October 25, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Satoshi Tobe, Yasushi Mizusawa
  • Publication number: 20110045246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Application
    Filed: May 7, 2009
    Publication date: February 24, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Publication number: 20110033958
    Abstract: The present invention provides a method for forming an oxide film on a silicon wafer, comprising: measuring surface roughness of the silicon wafer and/or crystallinity in a surface layer portion of the silicon wafer in advance; adjusting oxidizing conditions for the silicon wafer based on the measurement value; and forming the oxide film on the silicon wafer under the adjusted oxidizing conditions. As a result, there can be provided the method for forming an oxide film by which the oxidizing conditions can be adjusted based on a state of the surface and/or the surface layer of the silicon wafer before forming the oxide film and even an ultrathin oxide film can be thereby accurately formed.
    Type: Application
    Filed: March 24, 2009
    Publication date: February 10, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Satoshi Tobe, Yasushi Mizusawa
  • Publication number: 20100022038
    Abstract: The present invention provides a method for evaluating a semiconductor wafer, including at least: forming an oxide film on a front surface of a semiconductor wafer; partially removing the oxide film to form windows at two positions; diffusing a dopant having a conductivity type different from a conductivity type of a semiconductor as an evaluation target through the windows at the two positions and forming diffused portions in the semiconductor as the evaluation target to form PN junctions; and performing leakage current measurement and/or DLTS measurement in a part between the two diffused portions to evaluate the semiconductor wafer. As a result, there is provided the method for evaluating a semiconductor wafer that can perform junction leakage current measurement or DLTS measurement to easily evaluate a quality of the inside of the semiconductor wafer. In particular, there can be provided the method that can evaluate not only a PW or an EPW but also the inside of an SOI layer of an SOI wafer.
    Type: Application
    Filed: October 18, 2007
    Publication date: January 28, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventors: Tsuyoshi Ohtsuki, Kazuhiko Yoshida
  • Patent number: 7633305
    Abstract: The present invention is a method for evaluating a semiconductor wafer by measuring an electric characteristic of the semiconductor wafer by using a mercury electrode, wherein when the semiconductor wafer is held on a wafer chuck that the mercury electrode is formed in a holding surface of so that a side of a surface to be measured of the semiconductor wafer is set to a side of the wafer chuck, the semiconductor wafer is held on the wafer chuck whose diameter forming an outermost periphery of the holding surface is smaller than a diameter forming an outermost periphery of the surface to be measured of the semiconductor wafer, and then, the electric characteristic is measured by contacting the mercury electrode with the surface to be measured of the wafer, and an evaluation apparatus.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: December 15, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Hideki Sato
  • Patent number: 7525327
    Abstract: An apparatus for evaluating an electric characteristic of a semiconductor wafer including, at least, a wafer cassette section on which a wafer cassette for storing the semiconductor wafer that is an object to be evaluated is placed, a wafer pretreatment section for pretreating the semiconductor wafer in order to evaluate the electric characteristic thereof, a mercury probe section for evaluating the electric characteristic of the semiconductor wafer by using a mercury probe, and an automatic transport part for transporting the semiconductor wafer to each of the sections.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: April 28, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Hideki Sato
  • Publication number: 20080054920
    Abstract: The present invention is a method for evaluating an SOI wafer by using a mercury probe, comprising at least steps of, subjecting the SOI wafer to a hydrofluoric acid cleaning treatment and thereby to remove a native oxide film formed in a surface of the SOI wafer, next subjecting the native oxide film-removed SOI wafer to a treatment for stabilizing charge state, then contacting the charge-state stabilizing-treated SOI wafer with the mercury probe, and thereby evaluating the SOI wafer. Thereby, there can be provided an evaluation method in which a large-scale apparatus and multiple steps such as a photolithography process are not required and by which an electric characteristic of an SOI wafer can be measured simply and high-precisely in a short time and operation rate of measurement apparatus is improved and thereby the SOI wafer can be effectively evaluated.
    Type: Application
    Filed: May 31, 2005
    Publication date: March 6, 2008
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Hideki Sato
  • Publication number: 20070279080
    Abstract: The present invention is a method for evaluating a semiconductor wafer by measuring an electric characteristic of the semiconductor wafer by using a mercury electrode, wherein when the semiconductor wafer is held on a wafer chuck that the mercury electrode is formed in a holding surface of so that a side of a surface to be measured of the semiconductor wafer is set to a side of the wafer chuck, the semiconductor wafer is held on the wafer chuck whose diameter forming an outermost periphery of the holding surface is smaller than a diameter forming an outermost periphery of the surface to be measured of the semiconductor wafer, and then, the electric characteristic is measured by contacting the mercury electrode with the surface to be measured of the wafer, and an evaluation apparatus.
    Type: Application
    Filed: September 12, 2005
    Publication date: December 6, 2007
    Applicant: SHIN-ETSU HANDOTAI CO.,LTD.
    Inventors: Tsuyoshi Ohtsuki, Hideki Sato
  • Publication number: 20070273397
    Abstract: The present invention is an apparatus for evaluating a semiconductor wafer in order to evaluate an electric characteristic thereof, comprising, at least, a wafer cassette section on which a wafer cassette for storing the semiconductor wafer that is an object to be evaluated is placed, a wafer pretreatment section for pretreating the semiconductor wafer in order to evaluate the electric characteristic thereof, a mercury probe section for evaluating the electric characteristic of the semiconductor wafer by using a mercury probe, and an automatic transport part for transporting the semiconductor wafer to each of the sections. Thereby, there is provided an evaluation apparatus by which when an electric characteristic of a semiconductor wafer is evaluated, the electric characteristic of the semiconductor wafer or the like can be accurately evaluated with preventing contamination such as particles from adhering to a main surface of the semiconductor wafer and further the evaluation efficiency is high.
    Type: Application
    Filed: June 13, 2005
    Publication date: November 29, 2007
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Hideki Sato
  • Patent number: 6541117
    Abstract: There is disclosed a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein Erratic phenomenon does not occur in a MOS device fabricated on the silicon epitaxial wafer, a silicon epitaxial wafer having oxide dielectric breakdown voltage of 20 MV/cm or more, a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein oxygen concentration at an interface between the epitaxial layer and the silicon wafer of the silicon epitaxial wafer is 1×1017 to 1×1018 atoms/cm3 or 5×1016 to 5×1017 atoms/cm3, a method for producing a silicon epitaxial wafer comprising subjecting a silicon wafer to heat treatment in a hydrogen atmosphere, and then growing an epitaxial layer on the silicon wafer wherein the initial oxygen concentration of the silicon wafer, the heat treatment temperature and the heat treatment time of the heat treatment are predetermined so that oxygen concentration at an interface between the epitaxial layer and the silicon w
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: April 1, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Tsuyoshi Ohtsuki