Abstract: An element isolation structure of a semiconductor device that prevents travel of ions through an isolation film at the time of ion implantation during an element formation step, and also prevents break of the isolation film in the event of misalignment of a contact hole during an interconnection formation step are provided. The semiconductor device includes an isolation film formed on a main surface of a silicon substrate, and a protective nitride film formed on the isolation film. An upper surface of the isolation film is higher in level than the main surface of the silicon substrate. The protective nitride film is positioned, as seen from above, inner than a portion of the isolation film exposed on the main surface of the silicon substrate.

Abstract: A first pattern forming a memory cell is provided on a memory cell region, and a second pattern consisting of a film containing nitrogen atoms is provided on the first pattern. A third pattern forming a gate electrode of a transistor so that the height between the main surface of a semiconductor substrate and the surface of the third pattern is lower than the first pattern is provided on a peripheral circuit region, and a fourth pattern consisting of a film containing nitrogen atoms having a larger thickness than the second pattern is provided on the third pattern in correspondence to the third pattern. The thickness of a portion of the interlayer dielectric film located between the second pattern and a second conductive layer is smaller than the thickness of a portion of the interlayer dielectric film located between the fourth pattern and the second conductive layer.

Abstract: A first planetary gear unit is arranged to convert an input rotation from an input shaft to an output rotation whose speed is lower than that of the input rotation. A first unit including second and third planetary gear units is arranged between the first planetary gear unit and the output shaft. The first unit is arranged to provide, by managing the output rotation from the first planetary gear unit, the output shaft with seven types of rotation which respectively correspond to 6-forward speed and one reverse positions. A second unit is arranged between the first planetary gear unit and the first unit to manage a power transmission therebetween. One of the second and third planetary gear units is of a double ring type which comprises a sun gear powered by the first planetary gear unit, inside and outside ring gears concentrically disposed around the sun gear, pinions each being meshed with the sun gear and inside and outside ring gears, and a pinion carrier carrying the pinions.

Abstract: A first pattern forming a memory cell is provided on a memory cell region, and a second pattern consisting of a film containing nitrogen atoms is provided on the first pattern. A third pattern forming a gate electrode of a transistor so that the height between the main surface of a semiconductor substrate and the surface of the third pattern is lower than the first pattern is provided on a peripheral circuit region, and a fourth pattern consisting of a film containing nitrogen atoms having a larger thickness than the second pattern is provided on the third pattern in correspondence to the third pattern. The thickness of a portion of the interlayer dielectric film located between the second pattern and a second conductive layer is smaller than the thickness of a portion of the interlayer dielectric film located between the fourth pattern and the second conductive layer.

Abstract: It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard mask. A gate electrode (3) is formed by etching using a hard mask as a mask and the hard mask remains on an upper surface of the gate electrode (3) at a subsequent step. In the meantime, the upper surface of the gate electrode (3) can be therefore prevented from being unnecessarily etched. The hard mask is removed after ion implantation for forming a source-drain region. Consequently, the influence of the removal of the hard mask on a characteristic of a semiconductor device can be suppressed. In that case, moreover, a surface of a side wall (4) is also etched by a thickness of (d) so that an exposure width of an upper surface of the source-drain region is increased. After the removal of the hard mask, it is easy to salicide the gate electrode (3) and to form a contact on the gate electrode (3).

Abstract: A floor is partitioned into a plurality of areas S1 to S4 by a floor tunnel portion 11, side frames 13, side sills 12, and cross members 7, 8, 15, and 16, and the rigidity of the floor panels of the areas S1 to S3 is adjusted by rigidity adjustment portions 20, 21, 22, 23, and 25. These floor panels are set such that their natural frequency in a 2×1 mode, in which two antinodes are generated in the length direction of the automobile and one antinode is generated in the width direction of the automobile, is 240 to 260 Hz. Thus, a reduction in road noise due to automobile tire cavity resonance is achieved.

Abstract: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

Abstract: An element isolation structure of a semiconductor device that prevents travel of ions through an isolation film at the time of ion implantation during an element formation step, and also prevents break of the isolation film in the event of misalignment of a contact hole during an interconnection formation step are provided. The semiconductor device includes an isolation film formed on a main surface of a silicon substrate, and a protective nitride film formed on the isolation film. An upper surface of the isolation film is higher in level than the main surface of the silicon substrate. The protective nitride film is positioned, as seen from above, inner than a portion of the isolation film exposed on the main surface of the silicon substrate.

Abstract: The present invention relates to a non-volatile semiconductor memory device, having the higher margin of the implanted ion passing through a source-to-drain electrode, as well as the excellent covering power of an embedded layer deposited in and above a groove within a field oxide region distributed at both the source-to-drain electrode and a source area. The present invention also provides a method for manufacturing the non-volatile semiconductor memory device.

Abstract: A semiconductor device 10 with Test Element Group (TEG) for estimating an interlayer dielectric includes a memory cell array. The memory cell array includes a semiconductor substrate 1, and a floating gate 2, an interlayer dielectric 3, and a control gate 4, all formed on the substrate 1 in this order. The TEG has the memory cell array similar to semiconductor device subject to estimation for the interlayer dielectric 3. The floating gate 2 has an electrode 5 for estimating the interlayer dielectric 3 provided on at least one side against an elongated direction of the memory cell array.

Abstract: A semiconductor device 10 with Test Element Group (TEG) for estimating an interlayer dielectric includes a memory cell array. The memory cell array includes a semiconductor substrate 1, and a floating gate 2, an interlayer dielectric 3, and a control gate 4, all formed on the substrate 1 in this order. The TEG has the memory cell array similar to semiconductor device subject to estimation for the interlayer dielectric 3. The floating gate 2 has an electrode 5 for estimating the interlayer dielectric 3 provided on at least one side against an elongated direction of the memory cell array.

Abstract: A surface defect inspection apparatus includes a light radiation source, arranged to oppose a surface to be inspected serving as a mirror surface, for radiating light having a predetermined change pattern toward the surface to be inspected, a camera mechanism for receiving an image of the light radiation source, reflected by the surface to be inspected and forming a received-light image corresponding to the change pattern of the light radiation source, and a discriminator for discriminating a surface defect portion on the surface to be inspected by discriminating a portion whose change pattern is different from the change pattern on the basis of the received-light image formed by the camera mechanism.