Abstract: A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.

Abstract: Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

Abstract: Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.

Abstract: An electronic flight bag (EFB) system for use on a mobile platform, for example, a commercial or military aircraft. The EFB system includes first and second independent processors that run first and second independent software applications. The first software application may be a Type C application requiring a high level of governmental agency certification for use on an aircraft while the second application may be a commercially available, off-the-shelf software application that requires no certification. The two processors share a common display, although the first processor is provided with control over the display so that use of the display by the second processor can be inhibited or limited by the first processor as may be needed to display more critical flight or aircraft related information. The first processor is also provided with control over a switching subsystem that can interrupt the flow of information from external I/O devices to and from the second processor, if needed.

Abstract: A computer-implemented method performs foreground segmentation of an input image. The method receives a first foreground segmentation at a first resolution of the input image and determines a plurality of labelled seed points based on the first foreground segmentation of the input image. The method associates each of the plurality of pixels in the input image with one of the determined labelled seed points to obtain a second foreground/background segmentation of the input image, and performs foreground separation on the input image at a second resolution by classifying each of the segments of the second segmentation as one of foreground and background based on the label of the associated seed point.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.

Abstract: Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P? region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P? region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P? region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

Abstract: A NAND flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates.

Abstract: Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines.

Abstract: A NAND flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits.

Abstract: A blade device enclosure has a chassis configured to selectively house a plurality of configurations of full-high and half-high blade devices, an administrator module, and at least one input/output device. The blade device enclosure also has a printed circuit board including a passive high-speed midplane configured to electronically couple the blade devices to the administrator module and the at least one input/output device.

Abstract: A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.

Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.

Abstract: A system and method for allowing flexible and simultaneous updates to database objects from one or more users is disclosed. The system may receive a change request to the object from the first user and then from a second user. The system may determine if the object is locked and, if so, informing the first user. If an edit request is received from the second user, the second user may be provided with multiple options, such as incorporating changes made by first user and overwriting changes made by second user with changes made by first user, incorporating changes made by first user and overwriting changes made by first user with changes made by second user, and cancelling changes made by second user.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements.

Abstract: Non-volatile storage elements having a P?/metal floating gate are disclosed herein. The floating gate may have a P? region near the tunnel oxide, and may have a metal region near the control gate. A P? region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P? region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

Abstract: A system and method for allowing flexible and simultaneous updates to database objects from one or more users is disclosed. The system may receive a change request to the object from the first user and then from a second user. The system may determine if the object is locked and, if so, informing the first user. If an edit request is received from the second user, the second user may be provided with multiple options, such as incorporating changes made by first user and overwriting changes made by second user with changes made by first user, incorporating changes made by first user and overwriting changes made by first user with changes made by second user, and cancelling changes made by second user.

Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

Abstract: In an embodiment, a method of providing an arranged display of data associated with a set of time periods is presented. In this method, values of a first data type are accessed, the values being observed during each of multiple time periods. An order for the time periods is determined based on the values of the first data type. A selectable region for each of the time periods is displayed, the regions being arranged according to the order. In response to a user selection of one of the selectable regions, a value of a second data type is displayed, the value of the second data type being observed during the time period of the selected one of the selectable regions.