Abstract: Switch card apparatus are disclosed. In one embodiment, a circuit includes a first portion having a first switch adapted to be coupled to a first voltage, a second portion including a second switch, and a third portion including a third switch. The first portion activates the first switch to couple the first voltage to the second portion. Similarly, the second portion activates the second switch in response to a second input signal and the first voltage to couple a second voltage to the third portion. Finally, the third portion activates the third switch in response to a third input signal and in response to the second voltage from the second portion to couple a control voltage to a load. Embodiments of the invention provide the desired reliability suitable for a variety of electrical systems, including arming and firing applications over a wide voltage and wide current range.

Abstract: Systems and methods relating to a properly dosed fabric, such as non woven fiber, are provided. In one aspect, the invention relates to a method for manufacturing a cloth having a consistent amount of medication thereon. In one embodiment, the weight and dimensions of the raw materials and the resulting cloths are compared to adjust the amount of solution that is applied to the fabric. In another embodiment, a continuous sheet of fabric is divided at select locations depending on its weight and physical dimensions. In one such embodiment, a controller may be utilized to determine the amount of tension to apply on the continuous non-woven fabric. In yet another embodiment, the tension applied to the fabric alters the physical dimensions of the fabric. Another aspect of the invention relates to a cloth of fibrous material, such as a non-woven cloth having a predetermined quantity of medication disposed thereon.

Abstract: A fast image region partition method receives a component labeled image and performs a two pass Zone Of Influence (ZOI) creation method to create a Zone Of Influence (ZOI) image. The two pass ZOI creation method performs a first pass scan to create a first pass intermediate distance image and a shortest distance component label image. It then performs a second pass scan using the first pass intermediate distance image and the shortest distance component label image to create a background distance transform image and a updated shortest distance component label image. An adaptive image region partition method receives a component labeled image and performs an adaptive two pass ZOI creation method to create an adaptive ZOI image. The distance lengths of the two pass adaptive ZOI creation method depend on their associated component labels. An adaptive cell segmentation method receives a nuclei mask image and a cell mask image.

Abstract: A BISR scheme which provides for on-chip assessment of the amount of repair on a given memory and for the flagging of any device as a fail when the device exceeds a pre-determined limit. Preferably, a counter is built and loaded through a test pattern during production testing, and the counter establishes the threshold for pass/fail criteria. The BISR is configured to load a repair solution and then test the memories for any additional failures and if there are any, repair them (provided enough redundant elements are available). In addition, a reliability controller for BISR designs can be provided, where the reliability controller contains a register set and a number of counters at the chip-level which can be loaded through a test pattern during production tests, where one of the counters contains the number of memories to be allowed for repair.

Abstract: A method and apparatus are disclosed for asynchronous testing of multiport memories. In one embodiment, the apparatus includes a built-in self-test (BIST) unit coupled to a multiport memory module and configured to apply a pattern of read and write test operations concurrently to multiple ports of the memory. The pattern of test operations may be any standard or customized pattern designed to establish the functionality of the multiport memory. The test operations to different ports are clocked by different clock signals so that the clock signals may be offset relative to each other by an adjustable or preset clock skew. Certain clock skews cause transitions to occur on signal lines in the memory array at the most sensitive portion(s) of a read cycle. The timing of these transitions, in combination with the presence of high-resistivity bridge faults, sufficiently disturbs the read cycle so as to cause a read error, thereby enabling detection of the bridge faults.

Abstract: A system for disabling defective memory elements includes a memory array, an address decoder and a decoder element. The memory array has multiple memory elements for storing data. The address decoder receives a requested memory address and produces multiple element-select signals. Each element-select signal is associated with one of the memory elements and indicates whether access to the associated memory element is requested by the host. The decoder element receives one of the element-select signals and provides an output signal to the associated memory element. If the associated memory element is functional, the output signal enables or disables the associated memory element in accordance with the associated element-select signal. If, on the other hand, the associated memory element is defective, the output signal disables the associated memory element regardless of the associated element-select signal.

Abstract: A graphics computer programming language, called the BDT Language, is disclosed for the description of three-dimensional objects and real-time interactions among them in a three-dimensional space. The BDT Language consists of a User Level Command Script and a corresponding Language Level Program Code. The User Level Command Script consists of command lines each having a mnemonical name followed by a list of arguments. The Language Level Program Code consists of a corresponding number of program lines each having an operation code for the command followed by a list of arguments. The Language Level Program Code is further compressed into a BDT File for efficient storage and download for viewing by a client user with a Web Browser. A BDT Interpreter is also devised to parse the BDT File into instructions for a separate display Engine for final rendition into the originally created set of three-dimensional objects.

Abstract: A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in the array. A comparator within the BIST or external to the BIST compares the actual output of the memory array to the expected output, and asserts an error signal whenever a mismatch occurs. The BISR unit intercepts addresses directed to the memory array, and operates on the addresses in three distinct phases. During a training phase, the BISR unit stores the intercepted addresses when the error signal is asserted. During the normal operation phase, the BISR unit compares all intercepted addresses to stored addresses and redirects a corresponding memory access if any intercepted address matches a stored address.

Abstract: A low-complexity method and apparatus for generating address sequences for the moving inversion test method. In one embodiment, the address sequence generator includes a ring of counter cells in which each cell is configured to provide a toggle signal to a subsequent cell. Each cell receives a distinct least significant bit selector signal which, when asserted, designates the subsequent cell as the least significant bit. When the least significant selector signal is asserted, the cell continuously asserts the toggle signal to the subsequent cell. When the selector signal is de-asserted, the cell asserts the toggle signal to the subsequent cell half as often as the toggle signal from the preceding cell. Each cell provides an output address bit which is toggled whenever the toggle signal from the preceding bit is asserted across a transition in a clock signal. This configuration causes the ring of cells to implement a counter with a selectable least significant bit.

Abstract: Accordingly, there is disclosed herein a fast word compare circuit suitable for use in a BIST or BISR environment. In one embodiment, the comparator includes a front end and a zero-detector circuit. The front end receives two or more words and compares them bitwise, generating a set of bit match signals that indicate which bits match. The zero detector receives the bit match signals from the front end and asserts an output signal when all the bit match signals indicate a match. The front end may consist of a set of exclusive-or (XOR) gates, each configured to generate a bit match signal from respective bits of the input words. The zero detector may include a set of bit transistors coupled in parallel between a first node and ground. Each bit transistor receives a respective bit match signal and conducts when the respective bit match signal is asserted.

Abstract: An information circuit in a semiconductor device suitable for encoding and retrieving a bit of information. The information circuit includes an input circuit and an output circuit. The input circuit includes an input node coupled to an input terminal of a transistor. The output circuit includes a load device, a fuse circuit, and first and second output terminals of the transistor all coupled in series between a power supply terminal and a ground terminal. The impedance of said fuse circuit is preferably alterable between an initial impedance and an altered impedance. An output node of said information circuit is coupled to said output circuit. The information circuit is configured such that the output node voltage is indicative of said impedance of said fuse circuit when said input node is biased to a “read” state, said power supply terminal is biased to a power supply voltage, and said ground terminal is grounded.

Abstract: A method for testing refresh operations of a memory array wherein subthreshold leakage current may be set to near worst-case conditions. The memory array includes a first row of memory cells having a first memory cell configured to store a first memory value, and a second row of memory cells having a second memory cell configured to store a second memory value. The method comprises storing a logic high value to the first memory cell as the first memory value, followed by storing a logic low value to the second memory cell as the second memory value. The method further comprises repeatedly driving a write bit line coupled to both the first and second memory cells at a logic low level for a period of a time equal to a refresh interval corresponding to the first memory cell. Additionally, the method includes subsequently reading the first memory value from the first memory cell.

Abstract: A computer receives image data from a star-shaped optical target in the object plane and calculates angle-dependent boundary sharpness. The horizontal, x-direction, amplitude derivative and the vertical, y-direction, amplitude derivative are computed over a portion of each star pattern image from a Z panning sequence. A microscope slide stage, carrying the target, is moved vertically from a level just below where the target is in focus to a level just above where the target is in focus. For each small increment of vertical motion, Z panning, an image of the star pattern is captured for analysis. Computations are performed on the differentiated images to search for evidence of elongation of the point spread function and variation with stage Z position of the angle of long axis of such an out-of-round point spread function. The presence of a distorted point spread function that varies along the optical axis indicates astigmatism.

Abstract: A computer receives image data from a star-shaped optical target in the object plane and calculates angle-dependent boundary sharpness. The horizontal, x-direction, amplitude derivative and the vertical, y-direction, amplitude derivative are computed over a portion of each star pattern image from a Z panning sequence. A microscope slide stage, carrying the target, is moved vertically from a level just below where the target is in focus to a level just above where the target is in focus. For each small increment of vertical motion, Z panning, an image of the star pattern is captured for analysis. Computations are performed on the differentiated images to search for evidence of elongation of the point spread function and variation with stage Z position of the angle of long axis of such an out-of-round point spread function. The presence of a distorted point spread function that varies along the optical axis indicates astigmatism.

Abstract: A computer receives image data from a star-shaped optical target in the object plane and calculates angle-dependent boundary sharpness. The horizontal, x-direction, amplitude derivative and the vertical, y-direction, amplitude derivative are computed over a portion of each star pattern image from a Z panning sequence. A microscope slide stage, carrying the target, is moved vertically from a level just below where the target is in focus to a level just above where the target is in focus. For each small increment of vertical motion, Z panning, an image of the star pattern is captured for analysis. Computations are performed on the differentiated images to search for evidence of elongation of the point spread function and variation with stage Z position of the angle of long axis of such an out-of-round point spread function. The presence of a distorted point spread function that varies along the optical axis indicates astigmatism.