Abstract: A write driver 100, 200, 300 is implemented to provide near-ground common mode output voltages to produce a more symmetrical head voltage swing (i.e. ±0.4V from ground to ±5V supply voltages). These features help to reduce the effects of common mode impedance associated with the interconnection to the disk drive head to improve overall performance. Lower jitter at high data rates can be achieved when compared to prior art techniques for implementing current mode write drivers. Further, the matched impedance between the write driver 100 and the interconnection 106 eliminates unwanted reflections. ECL level voltage swings (200–500 mV) have replaced more conventional CMOS level voltage swings (5V) to further reduce overall power dissipation associated with the write driver. The small ECL level switching further maintains constant power dissipation with changes in operating frequency and results in less NTLS effects due to quieter supplies.

Abstract: A write driver 100, 200, 300 is implemented to provide near-ground common mode output voltages to produce a more symmetrical head voltage swing (i.e. ±0.4V from ground to ±5V supply voltages). These features help to reduce the effects of common mode impedance associated with the interconnection to the disk drive head to improve overall performance. Lower jitter at high data rates can be achieved when compared to prior art techniques for implementing current mode write drivers. Further, the matched impedance between the write driver 100 and the interconnection 106 eliminates unwanted reflections. ECL level voltage swings (200-500 mV) have replaced more conventional CMOS level voltage swings (5V) to further reduce overall power dissipation associated with the write driver. The small ECL level switching further maintains constant power dissipation with changes in operating frequency and results in less NTLS effects due to quieter supplies.

Abstract: A write circuit selectively provides a write current through a write head in first and second opposite directions. The write circuit is connected to the write head by an interconnect, and has a positive supply level and a negative supply level. A first voltage source provides a first control voltage, and a second voltage source provides a second control voltage. A first resistor is provided between the first voltage source and the interconnect for impedance matching to the interconnect, and a second resistor is provided between the second voltage source and the interconnect for impedance matching to the interconnect. The first and second control voltages provide a transient voltage to the interconnect and provide a subsequent steady-state voltage to the interconnect.

Abstract: A read system for reading information from a storage medium and for providing an output signal to circuitry external from the read system is disclosed. The read system includes individual channel circuitry, a bias current generator for providing a bias current to the read system, and preamplifier circuitry connected between the bias current generator and the individual channel circuitry. The individual channel circuitry further includes a first and a second magnetoresistive element, a first and a second transistor, and a first and a second switch. The preamplifier circuit further includes a first and a second capacitor connected between a low potential and the first and second switches, respectively, and a third capacitor connected between the first and second capacitors. The preamplifier also includes a first and a second operational amplifier having an output connected to a base of the first transistor and a base of the second transistor.

Abstract: A voltage boost circuit for a write driver includes first and second semiconductor devices, such as Schottky diodes, coupled to respective first and second nodes to conduct write current through respective first or second current switches of the write driver when a forward voltage across the respective first or second semiconductor device exceeds a design voltage. The first and second current switches are responsive to respective complementary first and second input signals to direct write current in opposite directions through the winding between the first and second nodes. First and second storage devices are connected to the respective first and second semiconductor devices, and first and second buffers are responsive to a first state of the respective first and second input signals to operate the respective first or second storage device to increase the forward voltage across the respective first or second semiconductor device.

Abstract: An impedance matching circuit for a write driver matches the differential impedance of the winding of the write head and the transmission line to the write head. The impedance matching circuit includes a resistor connected between a node and a current switch of the write driver. The resistor has an impedance value matching the differential impedance value of the transmission line and head. During quiescent or steady state operation, the write driver provides a DC write current in a selected direction through the winding, and the resistor matches the differential impedance of the head and transmission line. During switching to reverse direction of write current through the winding, however, the resistor dampens voltage swings at the node to minimize current undershoot. Optionally, a capacitor is in parallel with the resistor to short-circuit the resistor during switching to improve the rise-time characteristics of the current reversal, but at a sacrifice of the impedance characteristics during switching.

Abstract: A read system for receiving information from a storage medium and for supplying a signal to circuitry external to the read system is disclosed. The read system includes a bias current generator, individual channel circuitry, and preamplifier circuitry. The individual channel circuitry further includes a first and a second magnetoresistive element. A plurality of transistors are connected to the first and the second magnetoresistive element and are cross-coupled to each other to cancel out any noise arising from a mismatch of the first and the second magnetoresistive element. The preamplifier circuitry further includes a first gain stage and a second gain stage separated by a first and a second capacitor. The first and the second capacitors permit an AC signal from the first gain stage to the second gain stage, while blocking unwanted DC signals which are necessary to properly bias the first and the second MR element.

Abstract: A write driver circuit for selectively controlling a direction of write current flow through a magnetic head having an inductive coil includes a source of first and second write currents. A forward drive switch directly sinks the first write current and sinks the second write current through the coil in a first direction. A reverse drive switch directly sinks the second write current and sinks the first write current through the coil in a second direction opposite the first direction. A control circuit operates the forward and reverse drive switches so that write current flows through the coil in a selected direction. An overshoot reduction circuit may be provided to reduce write current overshoot through the coil. An active subcircuit generates a compensation signal based on a voltage across the head exceeding a predetermined threshold. The first and second write currents are adjusted in response to the active subcircuit based on the compensation signal.

Abstract: A preamplifier system for receiving information from at least one magnetoresistive head cell and for supplying a signal to circuitry external to the preamplifier system is disclosed. The preamplifier system includes a bias current generator, a first preamplifier gain stage, and a second preamplifier gain stage. The bias current generator is connected between a first potential and the magnetoresistive head cell for providing a bias current to the magnetoresistive head cell. The first and second preamplifier gain stages include multiple transistors, resistors, capacitors, and current sources. The combination of first and second preamplifier gain stages provide the proper amplification of a signal received from the head cell while eliminating an unwanted DC offset signal.

Abstract: A current driver for supplying write current to an inductive write head of a disk drive includes an H-switch and first and second damping circuits connected across the inductive head. Each damping circuit includes a first controlled resistor (such as a MOS transistor) connected across the head. A delay circuit is connected between a load terminal at one side of the head and the control terminal of the MOS transistor, and is responsive to a transient voltage at the load terminal to delay the transient voltage to the control terminal of the MOS transistor for a predetermined delay period. The MOS transistor is responsive to the delayed transient voltage to provide a predetermined electrical resistance across the head to dampen undershoot and ringing in the driver. The MOS transistor turns off when the voltage at the load terminals stabilizes, thereby removing the damping resistance from the circuit.

Abstract: A magnetoresistive sensor and preamplifier system for sensing magnetization patterns in a magnetic disk based digital data storage and retrieval memory with a grounded magnetoresistive sensor The signals from the magnetoresistive sensor are coupled by a coupling capacitor to a grounded differential amplifier. The structure of the coupling capacitor in a monolithic integrated circuit determines the passband for the system in passing the magnetoresistive sensor signals.

Abstract: A circuit is provided to switch a drive transistor in a write driver circuit controlled by a write control signal to direct write current in a selected direction through an inductive head. Current is selectively conducted from a control region of the drive transistor in response to switching of the write control signal. A first bias circuit limits voltage fluctuation at the control region of the drive transistor. A second bias circuit prevents saturation of the drive transistor.

Abstract: A power supply filter has a primary current source coupled to a node carrying a power supply signal. The second end of the primary current source is coupled to an impedance that is further coupled to a low voltage node. A differential amplifier having an inverting input, a non-inverting input, and an output, has its non-inverting input coupled to the junction between the impedance and the primary current source. The output of the differential amplifier carries the filtered power supply signal and is coupled to a capacitance. The capacitance is coupled between the output and a lower voltage. A feedback path is coupled between the output and the inverting input.

Abstract: An open-loop biasing circuit for a magnetoresistive element provides high common mode and power supply rejection. Two current sources are connected together by two conduction paths. A first conduction path has two impedances. One impedance is tied between the first current source and ground and the second impedance is tied between the second current source and ground. The second conduction path includes the magnetoresistive element. A capacitive path between the two current sources reduces power supply noise and a voltage follower reduces parasitic capacitance in the capacitive path.

Abstract: The present invention is a system for reading information stored on a plurality of disk surfaces. The system comprises a plurality of channels each containing a preamplifier having first and second terminals for connection to an MR head. A bias circuit is provided common to all of the plurality of channels. The preamplifier in each channel includes first and second channel select circuits responsive to first and second channel select signals and current output from the bias circuit to output currents based on the current's output from the bias circuit. The preamplifier in each channel also includes first and second complementary output transistor circuits responsive to the current's output from the first and second channel select circuits and to the first and second voltages to provide bias current through the respective MR head connected between the first and second terminals of the respective channel. The system is entirely symmetrical around ground for improved common mode rejection.

Abstract: A biasing circuit for a two terminal sensing element has two separate biasing elements. Both biasing elements are controlled by a transconductance feedback circuit that controls feedback currents based upon a voltage associated with the sensing element. Both biasing elements also receive an activation value from an activation circuit. The activation value activates both biasing elements directly, without using the feedback loop.

Abstract: A preamplifier and its associated biasing circuitry for connection to a magnetoresistive sensor having a first end and a second end is disclosed. The biasing circuitry properly biases the preamplifier such that the preamplifier can properly read signals from the sensor. The preamplifier includes a first transistor. A base of the first transistor is connected to the first end of the magnetoresistive sensor. An emitter of the second transistor is connected to the emitter of the first transistor. A collector of the third transistor is connected to the collector of the first transistor. A base of the fourth transistor is connected to the second end of the magnetoresistive sensor, while the collector of the fourth transistor is connected to the collector of the second transistor, and the emitter of the fourth transistor is connected to the emitter of the third transistor. The preamplifier further includes a voltage source and a first and a second resistor.

Abstract: An open-loop biasing circuit for a magnetoresistive element provides high common mode and power supply rejection. Two current sources are connected together by two conduction paths. A first conduction path has two impedances. One impedance is tied between the first current source and ground and the second impedance is tied between the second current source and ground. The second conduction path includes the magnetoresistive element. A capacitive path between the two current sources reduces power supply noise and a voltage follower reduces parasitic capacitance in the capacitive path.

Abstract: A first differential amplifier circuit is provided having a first and second input terminal suited for connection to a magnetic head. The first differential amplifier circuit includes first and second output terminals for providing a read output signal. A second differential amplifier circuit is provided which has first and second input terminals connected to the first and second input terminals, respectively, the first differential amplifier circuit. The second differential amplifier circuit also includes first and second output terminals. A first feedback capacitor is provided which is connected between the first input terminal of the first differential amplifier circuit and the first output terminal of the second differential amplifier circuit. A second feedback capacitor is provided which is connected between the second input terminal of the first differential amplifier circuit and the second output terminal of the second differential amplifier circuit.

Abstract: A write driver for a two-terminal inductive load comprises an H-bridge switching circuit and a push-pull driver circuit. The H-bridge switching circuit responds to a first mode to conduct a current in a first direction through the inductive load and responds to a second mode to conduct the current in a second direction through the inductive load. The push-pull driver circuit responds to the first mode to push a charge current into a first control node of the H-bridge and responds to the second mode to pull a discharge current from the first control node. In one form, the write driver includes a second push-pull driver circuit responsive to the first mode to pull a discharge current from a second control node and to the second mode to push a charge current into the second control node.