Patents by Inventor Tuhin Sinha

Tuhin Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200066669
    Abstract: A thermal interface material and systems and methods for forming a thermal interface material include depositing a layer of a composite material, including at least a first material and a second material, the first material including a carrier fluid and the second material including a filler particle suspended within the first material. A particle manipulator is positioned over the layer of the composite material, the particle manipulator including at least one emitter to apply a particle manipulating field to bias a movement of the filler particles. The second material is redistributed by applying the particle manipulating field to interact with the second material causing the second material to migrate from a surrounding region in the composite material into a high concentration region in the composite material to form a customized thermal interface such that the high concentration region is configured and positioned corresponding to a hotspot.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventors: Jonathan Fry, Tuhin Sinha, Michael Rizzolo, Bassem M. Hamieh
  • Patent number: 10553503
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 10541156
    Abstract: A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned within a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment receptacles within the lid with one or more respective alignment protrusions of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, respective lid pedestals may be loaded toward respective IC chips, and an integral lid foot may be loaded toward the carrier. While under compression, thermal interface material between respective lid pedestals and respective IC chips and seal band material between the integral foot and the carrier may be cured.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Marcus E. Interrante, Kathryn R. Lange, Kamal K. Sikka, Tuhin Sinha, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 10541211
    Abstract: A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tuhin Sinha, Krishna R. Tunga
  • Publication number: 20190357781
    Abstract: An embodiment of a method for assessing cardiovascular disease in a user with a body region using a mobile computing device including a camera module, includes receiving a time series of image data of a body region of the user, the time series of image data captured during a time period; generating a photoplethysmogram dataset from the time series of image data; generating a processed PPG dataset; determining a cardiovascular parameter value of the user based on the processed PPG dataset; fitting a chronobiological model to (1) the cardiovascular parameter value, and (2) a subsequent cardiovascular parameter value, characterizing a cardiovascular parameter variation over time of the user based on the fitted chronobiological model; and presenting an analysis of the cardiovascular parameter variation to the user at the mobile computing device.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventors: Tuhin Sinha, Ian Eslick, Alan Leggitt
  • Publication number: 20190357855
    Abstract: A method and system for acquiring data for assessment of cardiovascular disease, the method comprising one or more of: manipulating one or more hardware aspects of the photoplethysmography data acquisition system(s) implementing the method; manipulating or providing user experience/user interface (UX/UI) aspects of the system(s) implementing the method; acquiring, processing, and deriving insights population specific data; accounting for or controlling sampling site variability; and using other suitable sources of data in order to generate high quality data for characterization, assessment, and management of cardiovascular disease.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventors: Tuhin Sinha, Ian Eslick, Alan Leggitt
  • Patent number: 10420475
    Abstract: An embodiment of a method for assessing cardiovascular disease in a user with a body region using a mobile computing device including a camera module, includes receiving a time series of image data of a body region of the user, the time series of image data captured during a time period; generating a photoplethysmogram dataset from the time series of image data; generating a processed PPG dataset; determining a cardiovascular parameter value of the user based on the processed PPG dataset; fitting a chronobiological model to (1) the cardiovascular parameter value, and (2) a subsequent cardiovascular parameter value, characterizing a cardiovascular parameter variation over time of the user based on the fitted chronobiological model; and presenting an analysis of the cardiovascular parameter variation to the user at the mobile computing device.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 24, 2019
    Assignee: Vital Labs, Inc.
    Inventors: Tuhin Sinha, Ian Eslick, Alan Leggitt
  • Patent number: 10420515
    Abstract: A method and system for acquiring data for assessment of cardiovascular disease, the method comprising one or more of: manipulating one or more hardware aspects of the photoplethysmography data acquisition system(s) implementing the method; manipulating or providing user experience/user interface (UX/UI) aspects of the system(s) implementing the method; acquiring, processing, and deriving insights population specific data; accounting for or controlling sampling site variability; and using other suitable sources of data in order to generate high quality data for characterization, assessment, and management of cardiovascular disease.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: September 24, 2019
    Assignee: Vital Labs, Inc.
    Inventors: Tuhin Sinha, Ian Eslick, Alan Leggitt
  • Patent number: 10381276
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Patent number: 10249548
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Patent number: 10134649
    Abstract: A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20180301355
    Abstract: A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 18, 2018
    Inventors: Tuhin Sinha, Krishna R. Tunga
  • Patent number: 10068812
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 10008427
    Abstract: A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20180076101
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Patent number: 9911716
    Abstract: A lidded or lidless flip-chip package includes two or more polygon shaped dies. The polygon dies may be interconnected to a substrate or to an interposer interconnected to a substrate. The interposer may be similarly shaped with respect to the polygon die(s). For the lidless or lidded package, the package may include underfill under the polygon dies surrounding associated interconnects. For the lidded package, the package may also include thermal interface materials, seal bands, and a lid. The polygon die package reduces shear stress between the polygon die/interposer and associated underfill as compared to square or rectangular shaped die/interposer of the same area. The polygon dies further maximize the utilization of a wafer from upon which the polygon dies are fabricated. The multi polygon die package may allow for a significant reduction of the polygon die to polygon die relative to the spacing and may reduce signal interconnect time.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Taryn J. Davis, Tuhin Sinha
  • Publication number: 20180047644
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 15, 2018
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20180019172
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 18, 2018
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 9818655
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20170271219
    Abstract: A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha