Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: A method of patterning a substrate in accordance with an embodiment of the invention includes forming a plurality of openings within at least one of photoresist and amorphous carbon. The openings are of common outermost cross sectional shape relative one another. Individual of the openings have at least one lateral open dimension having a degree of variability among the plurality. The photoresist with the plurality of openings is exposed to/treated with a plasma effective to both increase the lateral open size of the openings and at least reduce the degree of variability of said at least one open dimension among the openings. Other aspects and implementations are contemplated.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching chemistry comprising Cl2 and CH2F2. A method of forming a variable resistance memory cell includes forming a conductive inner electrode material over a substrate. A variable resistance chalcogenide material comprising germanium, antimony, and tellurium is formed over the conductive inner electrode material. A conductive outer electrode material is formed over the chalcogenide material. The germanium, antimony, and tellurium-comprising material is plasma etched using a chemistry comprising Cl2 and CH2F2.

Abstract: A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching chemistry comprising Cl2 and CH2F2. A method of forming a variable resistance memory cell includes forming a conductive inner electrode material over a substrate. A variable resistance chalcogenide material comprising germanium, antimony, and tellurium is formed over the conductive inner electrode material. A conductive outer electrode material is formed over the chalcogenide material. The germanium, antimony, and tellurium-comprising material is plasma etched using a chemistry comprising Cl2 and CH2F2.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching chemistry comprising Cl2 and CH2F2. A method of forming a variable resistance memory cell includes forming a conductive inner electrode material over a substrate. A variable resistance chalcogenide material comprising germanium, antimony, and tellurium is formed over the conductive inner electrode material. A conductive outer electrode material is formed over the chalcogenide material. The germanium, antimony, and tellurium-comprising material is plasma etched using a chemistry comprising Cl2 and CH2F2.

Abstract: A method of patterning a substrate in accordance with an embodiment of the invention includes forming a plurality of openings within at least one of photoresist and amorphous carbon. The openings are of common outermost cross sectional shape relative one another. Individual of the openings have at least one lateral open dimension having a degree of variability among the plurality. The photoresist with the plurality of openings is exposed to/treated with a plasma effective to both increase the lateral open size of the openings and at least reduce the degree of variability of said at least one open dimension among the openings. Other aspects and implementations are contemplated.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.