Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: The invention includes a method of patterning a material over a semiconductive substrate, comprising: a) forming a layer of first material against a second material and over the substrate, the substrate comprising a surface having a center and an edge; b) first etching the first material in a reaction chamber, the first etching comprising a first center-to-edge uniformity across the surface of the wafer and comprising a first selectivity for the first material relative to the second material; c) second etching the first material in the reaction chamber, the second etching comprising a second selectivity for the first material relative to the second material, the second center-to-edge uniformity being less than the first center-to-edge uniformity, the second selectivity being greater than the first selectivity; and d) cleaning a component of the first material from at least one sidewall of the reaction chamber between the first and second etchings.

Abstract: In one embodiment, the invention includes a method of removing at least a portion of a material from a substrate. The method includes providing a substrate in a reaction chamber, the substrate having a material supported thereover, and first etching the material while the substrate is in the reaction chamber. The method also includes, after the first etching, cleaning a component from at least one sidewall of the reaction chamber while the substrate remains therein; the component comprising a species that is present in the material. The cleaning includes exposing the sidewall and substrate to conditions which substantially selectively remove the component from the sidewall while not removing the material from the substrate, and not etching any other materials supported by the substrate. After the cleaning, the method includes second etching the material while the substrate is in the reaction chamber.

Abstract: A processing method includes patterning a material over a semiconductive substrate having a center and an edge. The method includes forming a layer of first material against a second material and over the semiconductive substrate and first etching the first material in a reaction chamber. First etching provides a first center-to-edge uniformity across the wafer surface and a first selectivity for the first material relative to the second material. The method also includes second etching the first material to provide a second center-to-edge uniformity across the wafer surface and a second selectivity greater than the first selectivity for the first material relative to the second material. The second center-to-edge uniformity is less than the first center-to-edge uniformity. The method also includes cleaning a component of the first material from at least one sidewall of the reaction chamber between the first and second etchings.

Abstract: In one embodiment, the invention includes a method of removing at least a portion of a material from a substrate. The method includes providing a substrate in a reaction chamber, the substrate having a material supported thereover, and first etching the material while the substrate is in the reaction chamber. The method also includes, after the first etching, cleaning a component from at least one sidewall of the reaction chamber while the substrate remains therein; the component comprising a species that is present in the material. The cleaning includes exposing the sidewall and substrate to conditions which substantially selectively remove the component from the sidewall while not removing the material from the substrate, and not etching any other materials supported by the substrate. After the cleaning, the method includes second etching the material while the substrate is in the reaction chamber.

Abstract: A processing method includes patterning a material over a semiconductive substrate having a center and an edge. The method includes forming a layer of first material against a second material and over the semiconductive substrate and first etching the first material in a reaction chamber. First etching provides a first center-to-edge uniformity across the wafer surface and a first selectivity for the first material relative to the second material. The method also includes second etching the first material to provide a second center-to-edge uniformity across the wafer surface and a second selectivity greater than the first selectivity for the first material relative to the second material. The second center-to-edge uniformity is less than the first center-to-edge uniformity. The method also includes cleaning a component of the first material from at least one sidewall of the reaction chamber between the first and second etchings.

Abstract: The invention includes a method of patterning a material over a semiconductive substrate, comprising: a) forming a layer of first material against a second material and over the substrate, the semiconductive substrate comprising a surface having a center and an edge; b) first etching the first material in a reaction chamber, the first etching comprising a first center-to-edge uniformity across the surface of the wafer and comprising a first selectivity for the first material relative to the second material; c) second etching the first material in the reaction chamber, the second etching comprising a second selectivity for the first material relative to the second material, the second center-to-edge uniformity being less than the first center-to-edge uniformity, the second selectivity being greater than the first selectivity; and d) cleaning a component of the first material from at least one sidewall of the reaction chamber between the first and second etchings.