Abstract: A mobile phone device comprises the following: a processor; a first display controller for driving an internal display of the mobile phone device; and a second display controller for driving an external display, wherein the external display is connectable to the second display controller via a connector.

Abstract: A mobile phone device utilizing a first communications protocol and a second communications protocol, comprises: a first system having a general processor, a memory, a first communications system providing for the first communications protocol and utilizing a first communications protocol stack, and a first link; a second system having a dedicated communications accelerator providing for the second communications protocol and utilizing a second communications protocol stack, and a second link; wherein the first link and the second link are connected; and wherein the memory in the first system holds the first communications protocol stack and the second communications protocol stack.

Abstract: Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.

Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

Abstract: A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase pulse count corresponding to a preliminary erase operation during which a relatively small portion of a sector is erased. The adjustment of the erase bias voltage in this manner enables the rest of the sector to be erased using erase bias voltages that are better suited to the current erase characteristics of the sector.

Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

Abstract: A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Abstract: A method for manufacturing a sputtering target includes the steps of: providing a highly pure matrix material containing a magnetic metal, and a highly pure precious metal ingot material; cleaning the surfaces of the matrix material and the precious metal ingot; vacuum melting the matrix material and the precious metal ingot to obtain a molten alloy; pouring the molten alloy in a mold having a cooling system while maintaining a surface of the molten alloy at a molten state by arc heating until the pouring is finished, thereby forming the molten alloy into a cast blank; hot working the cast blank; and annealing the cast blank after the hot working.

Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

Abstract: Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

Abstract: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

Abstract: An apparatus and a method for adaptively calculating a start position of a series of symbols are provided. The method is applied to a frame synchronization circuit that implements the apparatus for calculating the symbolic start position of a packet-switching communication system. Even under the situations such as higher frequency offset, the frequency offset value approaching zero or unstable frequency offset, the frame synchronization circuit using the claimed method still can estimate the symbolic start position. The preferred method includes a first step of retrieving the signals in a unit of packets, and calculating their delay correlation value. Next, a control circuit is incorporated to retrieve multiple groups of symbols, and to set the parameters of the systems as a basis for identifying the system's property. After that, it's to estimate the symbolic start position.

Abstract: An electronic storage card reader applied to a computer system includes a system port, a control chip, a first card insertion part, and a second card insertion part. The system port is connected to a computer system. The control chip is connected to the system port for converting and transmitting data with the computer system. Each of the first card insertion part and the second card insertion part includes a plurality of card insertion slots connected with the control chip and provided for inserting a memory card. The control chip independently accesses the memory cards inserted into the card insertion slots of the first card insertion part, integrates the memory cards inserted into the card insertion slots of the second card insertion part to form a merged storage space, and accesses the merged storage space. The invention allows the electronic storage card reader to have a single larger storage capacity.

Abstract: Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

Abstract: A bridging device with power-saving function includes first and second interfaces, first and second physical layer processing devices, and a controller. The first interface is utilized for coupling a first external device complying with the first interface. The first external device receives a device request signal, and accordingly sends back a device response signal through the first physical layer processing device. The second interface is utilized for coupling a second external device complying with the second interface. The controller is coupled between the first and the second physical layer processing device for transmitting the device request signal with the predetermined frequency to the first physical layer processing device in order to receive the device response signal. When the controller does not receive the device response signal, the controller turns the second physical layer processing device off.

Abstract: A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality of wordlines are formed of p+ polysilicon. A second select gate that has a width of 140 nm or less is coupled to the plurality of wordlines.

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract: A memory device includes a substrate and a first dielectric layer formed over the substrate. At least two charge storage elements are formed over the first dielectric layer. The substrate and the first dielectric layer include a shallow trench filled with an oxide material. The oxide material formed in a center portion of the shallow trench is removed to provide a region with a substantially rectangular cross-section.

Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Abstract: A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.