Patents by Inventor Tung-Ching Tseng

Tung-Ching Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365428
    Abstract: An apparatus for wafer processing includes a wafer pedestal configured to support a wafer, a radiation source configured to provide an electromagnetic radiation to the wafer, and a transparent window disposed between the wafer pedestal and the radiation source. The transparent window has a first zone having a first rough surface, and an Ra value of the first rough surface is between approximately 0.5 ?m and approximately 100 ?m. The apparatus for wafer processing further includes a primary reflector disposed in the radiation source, and a secondary reflector disposed between the transparent window and the radiation source. The rough surface can be provided over the transparent window, the primary reflector, and/or the secondary reflector.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Inventors: TUNG-CHING TSENG, SUNG-PO YANG, FENG-TAO LEE, SHIH FANG CHEN
  • Publication number: 20190136373
    Abstract: A chemical vapor deposition (CVD) apparatus is provided. The CVD apparatus includes a CVD chamber including multiple wall portions. A pedestal is disposed inside the CVD chamber, configured to support a substrate. A gas inlet port is disposed on one of the wall portions and below a substrate support portion of the pedestal. In addition, a gas flow guiding member is disposed inside the CVD chamber, coupled to the gas inlet port, and configured to dispense cleaning gases from the gas inlet port into the CVD chamber.
    Type: Application
    Filed: June 28, 2018
    Publication date: May 9, 2019
    Inventors: Chih-Hung YEH, Tsung-Lin LEE, Yi-Ming LIN, Sheng-Chun YANG, Tung-Ching TSENG
  • Patent number: 10121698
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Publication number: 20170194162
    Abstract: A semiconductor manufacturing equipment includes a processing chamber, at least one reflector and at least one electromagnetic wave emitting device. The reflector is present in the processing chamber. The electromagnetic wave emitting device is present between the reflector and a wafer in the processing chamber. The electromagnetic wave emitting device is configured to emit a spectrum of electromagnetic wave to the wafer. The reflector has a relative reflectance to Al2O3 with respect to the spectrum of electromagnetic wave, and the relative reflectance of the reflector is in a range from about 70% to about 120%.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 6, 2017
    Inventors: Hsin-Chih LIU, Chia-Hung HUANG, Jen-Chung CHEN, Tung-Ching TSENG
  • Publication number: 20170125290
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Application
    Filed: January 16, 2017
    Publication date: May 4, 2017
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Patent number: 9548241
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Publication number: 20160181152
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Patent number: 9318364
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Publication number: 20150197849
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Patent number: 7297632
    Abstract: A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: November 20, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuang-Ping Hou, Syun-Ming Jang, Ying-Ho Chen, Chu-Yun Fu, Tung-Ching Tseng
  • Publication number: 20060211250
    Abstract: A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.
    Type: Application
    Filed: March 17, 2005
    Publication date: September 21, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuang-Ping Hou, Syun-Ming Jang, Ying-Ho Chen, Chu-Yun Fu, Tung-Ching Tseng
  • Patent number: 7109117
    Abstract: A method for chemical mechanical polishing (CMP) of a shallow trench isolation (STI) structure employs a sequence of slurry polishes. In the first step the substrate is polished with either silica-based slurry or diluted ceria-based slurry. The first polishing is at a higher removal rate than the second polishing step. The polishing proceeds with some planarization but does not expose the polish stop layer. After partial planarization, the high selectivity slurry was used to complete the process. Improved throughput, lower defects and good within wafer uniformity are achieved.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: September 19, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ching Tseng, Syun-Ming Jang, Li-Jia Yang, Chuan-Ping Hou
  • Patent number: 7016790
    Abstract: An in-line hot-wire sensor for monitoring the mixing and the flow rate of slurry is disclosed. The hot-wire sensor may include a number of resistors organized into a Wheatstone bridge, as well as a frequency-domain transform mechanism. The resistors include a hot-wire resistor that is placed in-line with the slurry after substances have been mixed to become the slurry. The Wheatstone bridge thus yields a signal that is transformed to the frequency domain by the frequency-domain transform mechanism, such as by performing a Fast Fourier Transform (FFT) of the signal. The frequency-domain transform is used to monitor the mixing of the substances into the slurry, and the flow rate of the slurry. The signal may be amplified prior to transformation to the frequency domain.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: March 21, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ching Tseng, Li-Jia Yang
  • Patent number: 6930040
    Abstract: In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over the intermediate structure. The isolation material fills the isolation trench. Excess isolation material extends above the top surface of the intermediate structure. Part of the excess isolation material is removed until there is a predetermined thickness of isolation material remaining on the top surface of the intermediate structure. A contact opening is formed in the isolation material at the isolation trench. The contact opening extends through at least part of the intermediate structure. Contact material is deposited over the isolation material. The contact material fills the contact opening. Excess contact material, if any, that extends above the isolation material is removed. The excess isolation material is removed at least until the top surface of the intermediate structure is reached.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: August 16, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Ping Hou, Syun-Ming Jang, Ying-Ho Chen, Tung-Ching Tseng
  • Publication number: 20050153555
    Abstract: A method for chemical mechanical polishing (CMP) of a shallow trench isolation (STI) structure employs a sequence of slurry polishes. In the first step the substrate is polished with either silica-based slurry or diluted ceria-based slurry. The first polishing is at a higher removal rate than the second polishing step. The polishing proceeds with some planarization but does not expose the polish stop layer. After partial planarization, the high selectivity slurry was used to complete the process. Improved throughput, lower defects and good within wafer uniformity are achieved.
    Type: Application
    Filed: January 14, 2004
    Publication date: July 14, 2005
    Inventors: Tung-Ching Tseng, Syun-Ming Jang, Li-Jia Yang, Chuan-Ping Hou
  • Publication number: 20050090096
    Abstract: In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over the intermediate structure. The isolation material fills the isolation trench. Excess isolation material extends above the top surface of the intermediate structure. Part of the excess isolation material is removed until there is a predetermined thickness of isolation material remaining on the top surface of the intermediate structure. A contact opening is formed in the isolation material at the isolation trench. The contact opening extends through at least part of the intermediate structure. Contact material is deposited over the isolation material. The contact material fills the contact opening. Excess contact material, if any, that extends above the isolation material is removed. The excess isolation material is removed at least until the top surface of the intermediate structure is reached.
    Type: Application
    Filed: October 22, 2003
    Publication date: April 28, 2005
    Inventors: Chuan-Ping Hou, Syun-Ming Jang, Ying-Ho Chen, Tung-Ching Tseng
  • Patent number: 6812069
    Abstract: A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 2, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Tung-Ching Tseng, Syun-Ming Jang, Chih-Hsiang Yao
  • Publication number: 20040115925
    Abstract: A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ching Tseng, Syun-Ming Jang, Chih-Hsiang Yao
  • Publication number: 20040083068
    Abstract: An in-line hot-wire sensor for monitoring the mixing and the flow rate of slurry is disclosed. The hot-wire sensor may include a number of resistors organized into a Wheatstone bridge, as well as a frequency-domain transform mechanism. The resistors include a hot-wire resistor that is placed in-line with the slurry after substances have been mixed to become the slurry. The Wheatstone bridge thus yields a signal that is transformed to the frequency domain by the frequency-domain transform mechanism, such as by performing a Fast Fourier Transform (FFT) of the signal. The frequency-domain transform is used to monitor the mixing of the substances into the slurry, and the flow rate of the slurry. The signal may be amplified prior to transformation to the frequency domain.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ching Tseng, Li-Jia Yang
  • Patent number: 6686284
    Abstract: A chemical mechanical polishing apparatus that is equipped with a chilled retaining ring and a method for using the apparatus are described. The retaining ring is mounted therein a heat transfer means such as a metal tube and flowing therethrough a heat exchanging fluid for carrying away heat from the wafer mounted in the retaining ring, resulting in a temperature reduction in the slurry solution that contacts the wafer. The present invention apparatus and method therefore reduces the delamination problem for low k dielectric materials during polishing and the wafer scratching problem.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: February 3, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chi-Wei Chung, Tung-Ching Tseng, Tsu Shih, Syun-Ming Jang