Abstract: In some embodiments, the present disclosure relates to a method that includes receiving an initial layout design for a circuit schematic. The initial layout design includes a first gate electrode, a second gate electrode, and a third gate electrode arranged over a continuous fin. A first source/drain region is arranged between the first gate electrode and dummy gate electrode, and a second source/drain region is arranged between the second gate electrode and the dummy gate electrode. The method further includes determining if at least one of the first or second source/drain regions corresponds to a drain in the circuit schematic, and modifying the initial layout design to increase a dummy threshold voltage associated with the dummy gate electrode when the at least one of the first or second source/drain regions corresponds to the drain in the circuit schematic to provide a modified layout design.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

Abstract: A method and structure for mitigating strain loss (e.g., in a FinFET channel) includes providing a semiconductor device having a substrate having a substrate fin portion, an active fin region formed over a first part of the substrate fin portion, a pickup region formed over a second part of the substrate fin portion, and an anchor formed over a third part of the substrate fin portion. In some embodiments, the substrate fin portion includes a first material, and the active fin region includes a second material different than the first material. In various examples, the anchor is disposed between and adjacent to each of the active fin region and the pickup region.

Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.

Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.