Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having a first pattern layer that includes first source/drain (S/D) contacts and second S/D contacts, the first and second S/D contacts are spaced away from each other by a spacing along a first direction, and each of the first and second S/D contacts have elongated shapes extending lengthwise in a second direction perpendicular to the first direction. The method includes constructing a conductive feature on a second pattern layer of the IC layout, the conductive feature having an initial rectangular shape with a length and a width, the length extending along the first direction. And the method includes modifying the conductive feature to form a modified conductive feature that is overlapped with the first S/D contacts and distanced away from the second S/D contacts.

Abstract: An IC includes a first standard cell (SC1) having a first circuit area (CA1) and a first transition area (TA1) placed on an edge of the CA1; and a SC2 having a CA2 and a TA2 placed on an edge of CA2?. CA1 includes a first and a second active region (AR1 and AR2) longitudinally oriented along a first direction (D1), and a first gate stack (G1) along a D2?D1 and extending over AR1 and AR2. G1 includes a first gate segment (GS1) contacting AR1 and a GS2 contacting AR2. GS1 and GS2 are different in composition. GS1 and GS2 are associated with a pFET and a nFET, respectively. TA1 includes a G2 longitudinally oriented along D2 and spans between opposite cell edges of the SC1. G2 is a lengthwise uniform gate stack. SC2 is placed in abutment with the SC1 such that TA1 and TA2 share a common edge.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a substrate having an n well abutting a p well along a boundary. The semiconductor structure also includes a continuous active region over the n well and the p well, a plurality of gate structures over channel regions of the continuous active region, and one gate structure of the plurality of gate structures is disposed directly over the boundary. A portion of the channel region directly under the one gate structure is in direct contact with both an n-type source/drain feature over the p well and a p-type source/drain feature over the n well.

Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction and having a first portion and a second portion separated from each other. The integrated circuit further includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit further includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, wherein the first section extends in the second direction. The conductive feature further includes a second section electrically connected to the second gate electrode structure, wherein the second section extends in the second direction. The conductive feature further includes a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

Abstract: Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.

Abstract: An integrated circuit (IC) layout design is received that includes a first circuit cell and a second circuit cell abutted to one another. The first circuit cell contains a first IC component, and the second circuit cell contains a second IC component. A determination is made that a distance between the first IC component and the second IC component is less than a predefined threshold when the first circuit cell and the second circuit cell are abutted together. The IC layout design is revised such that the distance between the first IC component and the second IC component is eliminated in the revised IC layout design.

Abstract: A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

Abstract: A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.

Abstract: The integrated circuit (IC) structure includes a semiconductor substrate, a first active region, a dummy fill region, a second active region, first metal gate structures, and second metal gate structures. The first active region is on the semiconductor substrate. The dummy fill region is on the semiconductor substrate. The second active region is on the semiconductor substrate and spaced apart from the first active region by the dummy fill region. The first metal gate structures extend in the first active region and have a first gate pitch and a first gate width. The second metal gate structures extend in the second active region and have a second gate width greater than the first gate width and a second gate pitch being an integer times the first gate pitch, and the integer being two or more.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. The method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.

Abstract: A method that includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block has a corner, adding first patterns along a first edge of the corner, adding second patterns along a second edge of the corner, moving a first column of the first patterns closest to the second edge horizontally toward the second edge, moving a second column of second patterns closest to the second edge horizontally toward the second edge, extending lengths of the first and second patterns in the first and second columns, and outputting a pattern layout in a computer-readable format, where the pattern layout includes the first patterns and the second patterns.

Abstract: A method includes forming first and second semiconductor fins protruding from a substrate. Each of the first and second semiconductor fins includes a stack of alternating channel layers and non-channel layers. The method also includes forming a dielectric helmet between and protruding from the first and the second semiconductor fins, forming a dummy gate stack over the dielectric helmet, patterning the dummy gate stack to expose a portion of the dielectric helmet, removing the exposed portion of the dielectric helmet, and forming a metal gate structure, such that a remaining portion of the dielectric helmet separates the metal gate structure between the first and the second semiconductor fins. The method also includes forming a contact feature over a portion of the metal gate structure. A sidewall of the contact feature is between one of the semiconductor fins and the remaining portion of the dielectric helmet.

Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers and the second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. Each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.

Abstract: Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.

Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

Abstract: A semiconductor structure includes a substrate having a first well of a first conductivity type and a second well of a second conductivity type. From a top view, the first well includes first and seconds edges extending along a first direction. The second edge has multiple turns, resulting in the first well having a protruding section and a recessed section. The semiconductor structure further includes a first source/drain feature over the protruding section and a second source/drain feature over a main body of the first well. The first source/drain feature is of the first conductivity type. The second source/drain feature is of the second conductivity type. The first and the second source/drain features are generally aligned along a second direction perpendicular to the first direction from the top view.