Abstract: A touch panel and a display apparatus. The touch panel has a touch region and a fingerprint identification region and includes a first metal mesh layer, a second metal mesh layer, and a dielectric layer. The first metal mesh layer includes a plurality of touch electrodes disposed in the touch region and a plurality of fingerprint identification electrodes disposed in the fingerprint identification region. The second metal mesh layer includes a plurality of fingerprint lead wires. Each of the plurality of fingerprint lead wires is electrically connected to corresponding one of the plurality of fingerprint identification electrodes. The dielectric layer is disposed between the first metal mesh layer and the second metal mesh layer. The dielectric layer is provided with a plurality of contact holes via which the identification lead wires are electrically connected to the fingerprint identification electrodes.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: A power amplifier includes an amplifying circuit, a feedback circuit and a grounding capacitor. The amplifier circuit includes at least a first transistor and a second transistor. A control terminal of the first transistor is configured to receive an input signal, a first terminal of the second transistor is coupled to the first transistor, and a second terminal of the second transistor is configured to generate an output signal. The feedback circuit is coupled to the control terminal of the first transistor and the second terminal of the second transistor. The ground capacitor is configured to couple the control terminal of the second transistor to ground. When a frequency of the input signal is between a first band and a second band, an amplification gain of the output signal relative to the input signal is substantially the same.

Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Abstract: A centrifugal fan is disclosed and includes a lower case, an impeller and an upper case. The lower case includes a bottom plate and a sidewall. The impeller is disposed on the bottom plate. The upper case is assembled with the sidewall to form an outlet. The upper case is formed by stamping and includes a first plane, an inlet and a grille. When the impeller is rotated, an airflow flowing from the inlet to the outlet is formed. The grille is protruded outwardly from the first plane, and includes a connecting frame and plural ribs. A spacing height is formed between the connecting frame and the inlet. Each rib has a first end connected to the connecting frame and a second end connected to the first plane. A pair of notches are disposed adjacent to two opposite lateral edges of the second end of the corresponding rib, respectively.

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.

Abstract: A heat dissipation assembly is disclosed and includes a frame and a fan. The frame includes a heat conduction channel and an airflow intake. The heat conduction channel is communication with an exterior through airflow intake. The frame includes a first plane, a second plane and an inclined plane. The first plane is disposed adjacent to the airflow intake. The inclined plane is connected between the first plane and the second plane. The second plane includes an inlet. The heat conduction channel is in communication between the airflow intake and the inlet. A cross-section area of the heat conduction channel adjacent to the airflow intake is greater than that of the heat conduction channel adjacent to the inlet. The fan is spatially corresponding to the inlet, and assembled with the frame to form an outlet in communication with the airflow intake and the heat conduction channel through the inlet.

Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.

Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.

Abstract: The present invention provides a chemical sensor comprising a substrate, a first colorimetric sensor array exposed and arranged in a first accommodating space of the substrate and a second colorimetric sensor array arranged in a second accommodating space of the substrate. The second accommodating space is covered with an isolating layer to isolates liquid molecules but allows gas molecules to pass through. The first colorimetric sensor array changes from a first initial color to a first indicating color according to a volatile part and a non-volatile part of an analyte, and the second colorimetric sensor array changes from a second initial color to a second indicating color according to the volatile part of the analyte, so that information of the volatile part and the non-volatile part of the analyte can be obtained simultaneously.

Abstract: The disclosure relates to an asymmetrical double-outlet blower, including an upper case, a lower case and an impeller. The upper case includes an inlet. The lower case and the upper case are assembled to form a housing having an accommodation space, and form a first outlet and a second outlet. The accommodation space is in fluid communication with the first outlet, the second outlet and the inlet. The first outlet and the second outlet are disposed on a lateral periphery of the housing and face two opposite directions, respectively. An opening cross-sectional area of the first outlet is less than an opening cross-sectional area of the second outlet. The impeller is accommodated within the accommodation space of the housing, spatially corresponding to the inlet, and rotated around a rotation axis. An airflow is inhaled through the inlet and transported to the first outlet and the second outlet, respectively.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: Preventing Transport Layer Security session man-in-the-middle attacks is provided. A first security digest generated by an endpoint device is compared with a second security digest received from a peer device. It is determined whether a match exists between the first security digest and the second security digest based on the comparison. In response to determining that a match does not exist between the first security digest and the second security digest, a man-in-the-middle attack is detected and a network connection for a Transport Layer Security session is terminated with the peer device.