Patents by Inventor Tung-I Lin

Tung-I Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079493
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: GUAN-QI CHEN, CHEN CHI HSIAO, KUN-TSANG CHUANG, FANG YI LIAO, YU SHAN HUNG, CHUN-CHIA CHEN, YU-SHAN HUANG, TUNG-I LIN
  • Patent number: 11610808
    Abstract: A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Pei Su, Tung-I Lin
  • Publication number: 20210305131
    Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.
    Type: Application
    Filed: June 11, 2021
    Publication date: September 30, 2021
    Inventors: Yu-Hung Cheng, Shih-Pei Chou, Yeur-Luen Tu, Alexander Kalnitsky, Tung-I Lin, Wei-Li Chen
  • Patent number: 11049797
    Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: June 29, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Shih-Pei Chou, Yeur-Luen Tu, Alexander Kalnitsky, Tung-I Lin, Wei-Li Chen
  • Patent number: 10971406
    Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Ching-Wei Tsai, Yeur-Luen Tu, Tung-I Lin, Wei-Li Chen
  • Publication number: 20210057270
    Abstract: A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: YU-HUNG CHENG, CHENG-TA WU, YEUR-LUEN TU, CHING-PEI SU, TUNG-I LIN
  • Publication number: 20200051871
    Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Yu-Hung CHENG, Ching-Wei TSAI, Yeur-Luen TU, Tung-I LIN, Wei-Li CHEN
  • Patent number: 10453757
    Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Ching-Wei Tsai, Yeur-Luen Tu, Tung-I Lin, Wei-Li Chen
  • Patent number: 10269864
    Abstract: Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Tung-I Lin, Wei-Li Chen, Yeur-Luen Tu
  • Patent number: 10147756
    Abstract: Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Yeur-Luen Tu, Tung-I Lin, Cheng-Lung Wu, Wei-Li Chen
  • Publication number: 20180269111
    Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Yu-Hung CHENG, Ching-Wei TSAI, Yeur-Luen TU, Tung-I LIN, Wei-Li CHEN
  • Publication number: 20180158863
    Abstract: Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 7, 2018
    Inventors: Yu-Hung Cheng, Tung-I Lin, Wei-Li Chen, Yeur-Luen Tu
  • Patent number: 9978650
    Abstract: A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Ching-Wei Tsai, Yeur-Luen Tu, Tung-I Lin, Wei-Li Chen
  • Patent number: 9905600
    Abstract: The present disclosure provides a method of manufacturing an image sensor device. The method includes: forming an etch stop layer on a first substrate; forming a light-sensing region comprising a light sensing quantum structure being able to detect a wavelength greater than about 1.5 um; forming a semiconductive substrate over the light-sensing region, the semiconductive substrate comprising an active component; forming an isolation structure extended through the light-sensing region; selectively removing the first substrate to expose the etch stop layer; and thinning the etch stop layer thereby exposing the light-sensing region.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Yeur-Luen Tu, Tung-I Lin, Cheng-Lung Wu
  • Patent number: 9899441
    Abstract: A method for manufacturing a deep trench isolation (DTI) structure with a tri-layer passivation layer is provided. An etch is performed into a semiconductor substrate to form a trench. A first undoped semiconductor layer is formed by epitaxy lining surfaces of the semiconductor substrate that define the trench. A doped semiconductor layer is formed by epitaxy over and lining the first undoped semiconductor layer in the trench. A second undoped semiconductor layer is formed by epitaxy over and lining the doped semiconductor layer in the trench. A structure resulting from the method is also provided.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Lung Wu, Tung-I Lin, Yeur-Luen Tu
  • Publication number: 20180047777
    Abstract: Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Inventors: Yu-Hung Cheng, Yeur-Luen Tu, Tung-I Lin, Cheng-Lung Wu, Wei-Li Chen
  • Patent number: 9887235
    Abstract: Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Tung-I Lin, Wei-Li Chen, Yeur-Luen Tu
  • Patent number: 9799702
    Abstract: Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Yeur-Luen Tu, Tung-I Lin, Cheng-Lung Wu, Wei-Li Chen
  • Publication number: 20170301611
    Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: YU-HUNG CHENG, SHIH-PEI CHOU, YEUR-LUEN TU, ALEXANDER KALNITSKY, TUNG-I LIN, WEI-LI CHEN
  • Publication number: 20170278893
    Abstract: Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Yu-Hung Cheng, Yeur-Luen Tu, Tung-I Lin, Cheng-Lung Wu, Wei-Li Chen