Patents by Inventor TUNG-JIUN WU

TUNG-JIUN WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035903
    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 4, 2021
    Inventor: TUNG-JIUN WU
  • Publication number: 20210028275
    Abstract: Provided are MIM capacitor and semiconductor structure including MIM capacitor. The MIM capacitor includes a dielectric structure, a bottom electrode on the dielectric structure, a first insulating layer covering the bottom electrode and the dielectric structure, a middle electrode stacked on the bottom electrode, a spacer, a second insulating layer and a top electrode. The middle electrode is separate from the bottom electrode by the first insulating layer therebetween. A bottommost surface of the middle electrode is lower than a top surface of the bottom electrode and higher than a bottom surface of the bottom electrode. The spacer is disposed on the first insulating layer and laterally aside and covers a sidewall of the middle electrode. The second insulating layer covers the middle electrode and the spacer. The top electrode is stacked on the middle electrode and separate from the middle electrode by the second insulating layer therebetween.
    Type: Application
    Filed: October 12, 2020
    Publication date: January 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Jiun Wu, Shun-Yi Lee
  • Patent number: 10879206
    Abstract: A semiconductor structure includes a first substrate including a die region and a scribe line region adjacent to the die region, a through substrate via disposed in the first substrate in the scribe line region, a first connecting structure disposed over the first substrate in the die region, a second connecting structure disposed over the first substrate in the scribe line region and coupled to the through substrate via, a first bonding structure disposed over the first substrate in the die region and coupled to the first connecting structure, and a second bonding structure disposed over the first substrate in the scribe line region and coupled to the second connecting structure. The through substrate via, the second connecting structure and the second bonding structure are physically and electrically separated from the first connecting structure and the first bonding structure.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Publication number: 20200402858
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate; forming a plurality of fin structures on the substrate; disposing a first dielectric layer over and between the plurality of fin structures; disposing a second dielectric layer over the first dielectric layer; removing a portion of the first dielectric layer and a portion of the second dielectric layer, wherein each of the plurality of fin structures is at least partially exposed through the first dielectric layer and the second dielectric layer; forming a gate structure over the plurality of fin structures; forming an interlayer dielectric (ILD) layer over the first dielectric layer and the second dielectric layer and around the gate structure; removing a portion of the ILD layer; and forming a contact extending into the ILD layer, wherein the contact is disposed above the second dielectric layer. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Inventor: TUNG-JIUN WU
  • Publication number: 20200402924
    Abstract: A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.
    Type: Application
    Filed: July 6, 2020
    Publication date: December 24, 2020
    Inventors: TUNG-JIUN WU, YINLUNG LU, MINGNI CHANG, MING-YIH WANG
  • Patent number: 10872821
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate; forming a plurality of fin structures on the substrate; disposing a first dielectric layer over and between the plurality of fin structures; disposing a second dielectric layer over the first dielectric layer; removing a portion of the first dielectric layer and a portion of the second dielectric layer, wherein each of the plurality of fin structures is at least partially exposed through the first dielectric layer and the second dielectric layer; forming a gate structure over the plurality of fin structures; forming an interlayer dielectric (ILD) layer over the first dielectric layer and the second dielectric layer and around the gate structure; removing a portion of the ILD layer; and forming a contact extending into the ILD layer, wherein the contact is disposed above the second dielectric layer. A semiconductor structure thereof is also provided.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: 10867944
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, a conductive pad, a passivation layer, a recess, a bump pad, and a conductive bump. The conductive pad is disposed over the substrate. The passivation layer is disposed over the substrate and partially covers the conductive pad. The recess extends through the passivation layer and extends at least partially into the conductive pad. The bump pad is disposed over the passivation layer and within the recess; and the conductive bump is disposed over the bump pad. A method of manufacturing the semiconductor structure is also provided.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Publication number: 20200381378
    Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Inventors: TUNG-JIUN WU, MINGNI CHANG, MING-YIH WANG, YINLUNG LU
  • Patent number: 10840324
    Abstract: The present disclosure provides a semiconductor structure, including a bottom terminal, a first middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer, a second middle terminal over the first middle terminal and separated from the first middle terminal by the high-k dielectric layer, a top terminal over the second middle terminal and separated from the second middle terminal by the high-k dielectric layer, a first via penetrating the bottom terminal and the second middle terminal, a second via penetrating the first middle terminal, a first passivation layer below the bottom terminal, and a second passivation layer over the top terminal.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: 10825765
    Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: 10825894
    Abstract: Provided are MIM capacitor and method of manufacturing the same. The MIM capacitor includes a first electrode, a second electrode, a third electrode, a first insulating layer, a second insulating layer, and a first spacer. The first electrode and the third electrode are electrically connected to each other. The first insulating layer is between the first electrode and the second electrode. The second insulating layer is between the second electrode and the third electrode. The first spacer is located between a sidewall of the first electrode and the first insulating layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Jiun Wu, Shun-Yi Lee
  • Patent number: 10804230
    Abstract: The present disclosure provides a semiconductor package, including a first conductive feature configured as an I/O terminal of the semiconductor package, a first passivation layer, a capacitor, and a second passivation layer. The first conductive feature includes a redistribution portion and a via portion. The maximum width of the redistribution portion along a first direction is more than 10 times the maximum width of the via portion along the first direction. The first passivation layer is surrounding the via portion of the first conductive feature. The capacitor is substantially within the first passivation layer and electrically coupled to the first conductive feature. The second passivation layer is formed on the first passivation layer and surrounding the redistribution portion of the first conductive feature. A method of manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Publication number: 20200312800
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, a conductive pad, a passivation layer, a recess, a bump pad, and a conductive bump. The conductive pad is disposed over the substrate. The passivation layer is disposed over the substrate and partially covers the conductive pad. The recess extends through the passivation layer and extends at least partially into the conductive pad. The bump pad is disposed over the passivation layer and within the recess; and the conductive bump is disposed over the bump pad. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventor: TUNG-JIUN WU
  • Publication number: 20200227368
    Abstract: A semiconductor structure includes a substrate; a conductive pad disposed over the substrate; a passivation disposed over the substrate and covering a portion of the conductive pad; a bump pad disposed over the conductive pad and the passivation; a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; and a dielectric member disposed over the passivation and surrounding the conductive pillar.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventor: TUNG-JIUN WU
  • Patent number: 10707179
    Abstract: A semiconductor structure including a MIM capacitor includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Jiun Wu, Yinlung Lu, Mingni Chang, Ming-Yih Wang
  • Publication number: 20200126935
    Abstract: The present disclosure provides a semiconductor package, including a first conductive feature configured as an I/O terminal of the semiconductor package, a first passivation layer, a capacitor, and a second passivation layer. The first conductive feature includes a redistribution portion and a via portion. The maximum width of the redistribution portion along a first direction is more than 10 times the maximum width of the via portion along the first direction. The first passivation layer is surrounding the via portion of the first conductive feature. The capacitor is substantially within the first passivation layer and electrically coupled to the first conductive feature. The second passivation layer is formed on the first passivation layer and surrounding the redistribution portion of the first conductive feature. A method of manufacturing the semiconductor package is also provided.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventor: TUNG-JIUN WU
  • Publication number: 20200105862
    Abstract: The present disclosure provides a semiconductor structure, including a bottom terminal, a middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer, a top terminal over the middle terminal and separated from the middle terminal by the high-k dielectric layer, and a silicon nitride layer over the top terminal and directly on the high-k dielectric layer.
    Type: Application
    Filed: January 31, 2019
    Publication date: April 2, 2020
    Inventor: TUNG-JIUN WU
  • Publication number: 20200075709
    Abstract: The present disclosure provides a semiconductor structure, including a bottom terminal, a first middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer, a second middle terminal over the first middle terminal and separated from the first middle terminal by the high-k dielectric layer, a top terminal over the second middle terminal and separated from the second middle terminal by the high-k dielectric layer, a first via penetrating the bottom terminal and the second middle terminal, a second via penetrating the first middle terminal, a first passivation layer below the bottom terminal, and a second passivation layer over the top terminal.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventor: TUNG-JIUN WU
  • Publication number: 20200035595
    Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 30, 2020
    Inventor: TUNG-JIUN WU
  • Publication number: 20190305078
    Abstract: Provided are MIM capacitor and method of manufacturing the same. The MIM capacitor includes a first electrode, a second electrode, a third electrode, a first insulating layer, a second insulating layer, and a first spacer. The first electrode and the third electrode are electrically connected to each other. The first insulating layer is between the first electrode and the second electrode. The second insulating layer is between the second electrode and the third electrode. The first spacer is located between a sidewall of the first electrode and the first insulating layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Jiun Wu, Shun-Yi Lee