Abstract: A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.

Abstract: A semiconductor structure includes a first dielectric layer, a first metal feature in the first dielectric layer, at least one etch stop layer on the first dielectric layer, a second dielectric layer on the at least one etch stop layer. The semiconductor structure further includes a first barrier sublayer on a sidewall of the second dielectric layer and the at least one etch stop layer, a second barrier sublayer on the first barrier sublayer and the first metal feature, and a second metal feature on the second barrier sublayer.

Abstract: A planarization dielectric layer is formed over the semiconductor device on a semiconductor substrate. A device contact via structure is formed through the planarization dielectric layer. A planar dielectric spacer liner is formed over the planarization dielectric layer, and is patterned to provide an opening over the device contact via structure. An etch stop dielectric liner and a via-level dielectric layer are formed over the planar dielectric spacer liner. An interconnect via cavity may be formed through the via-level dielectric layer by a first anisotropic etch process that may be selective to the etch stop dielectric liner, and may be subsequently extended by a second anisotropic etch process that etches the etch stop dielectric liner. An interconnect via structure may be formed in the interconnect via cavity. A bottom periphery of the interconnect via structure may be self-aligned to the opening in the planar dielectric spacer liner.

Abstract: A semiconductor structure includes a first dielectric layer, a first metal feature in the first dielectric layer, at least one etch stop layer on the first dielectric layer, a second dielectric layer on the at least one etch stop layer. The semiconductor structure further includes a first barrier sublayer on a sidewall of the second dielectric layer and the at least one etch stop layer, a second barrier sublayer on the first barrier sublayer and the first metal feature, and a second metal feature on the second barrier sublayer.

Abstract: Provided are MIM capacitor and semiconductor structure including MIM capacitor. The MIM capacitor includes a dielectric structure, a bottom electrode on the dielectric structure, a first insulating layer covering the bottom electrode and the dielectric structure, a middle electrode stacked on the bottom electrode, a spacer, a second insulating layer and a top electrode. The middle electrode is separate from the bottom electrode by the first insulating layer therebetween. A bottommost surface of the middle electrode is lower than a top surface of the bottom electrode and higher than a bottom surface of the bottom electrode. The spacer is disposed on the first insulating layer and laterally aside and covers a sidewall of the middle electrode. The second insulating layer covers the middle electrode and the spacer. The top electrode is stacked on the middle electrode and separate from the middle electrode by the second insulating layer therebetween.

Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.

Abstract: A planarization dielectric layer is formed over the semiconductor device on a semiconductor substrate. A device contact via structure is formed through the planarization dielectric layer. A planar dielectric spacer liner is formed over the planarization dielectric layer, and is patterned to provide an opening over the device contact via structure. An etch stop dielectric liner and a via-level dielectric layer are formed over the planar dielectric spacer liner. An interconnect via cavity may be formed through the via-level dielectric layer by a first anisotropic etch process that may be selective to the etch stop dielectric liner, and may be subsequently extended by a second anisotropic etch process that etches the etch stop dielectric liner. An interconnect via structure may be formed in the interconnect via cavity. A bottom periphery of the interconnect via structure may be self-aligned to the opening in the planar dielectric spacer liner.

Abstract: A method of manufacturing a semiconductor structure includes: forming an interconnect structure including a metallization layer over a substrate; depositing a first dielectric layer over the metallization layer; depositing a second dielectric layer over and separate from the first dielectric layer; depositing a third dielectric layer over the second dielectric layer, the third dielectric layer having a Young's modulus greater than that of the first and second dielectric layers; forming a capacitor structure over the third dielectric layer; and forming a conductive via extending through the capacitor structure and the first, second and third dielectric layers and electrically coupled to the metallization layer.

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor.

Abstract: A semiconductor structure includes a first dielectric layer, a first metal feature in the first dielectric layer, at least one etch stop layer on the first dielectric layer, a second dielectric layer on the at least one etch stop layer. The semiconductor structure further includes a first barrier sublayer on a sidewall of the second dielectric layer and the at least one etch stop layer, a second barrier sublayer on the first barrier sublayer and the first metal feature, and a second metal feature on the second barrier sublayer.

Abstract: A method of manufacturing a semiconductor structure includes: forming an interconnect structure including a metallization layer over a substrate; depositing a first dielectric layer over the metallization layer; depositing a second dielectric layer over and separate from the first dielectric layer; depositing a third dielectric layer over the second dielectric layer, the third dielectric layer having a Young's modulus greater than that of the first and second dielectric layers; forming a capacitor structure over the third dielectric layer; and forming a conductive via extending through the capacitor structure and the first, second and third dielectric layers and electrically coupled to the metallization layer.

Abstract: A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.

Abstract: A planarization dielectric layer is formed over the semiconductor device on a semiconductor substrate. A device contact via structure is formed through the planarization dielectric layer. A planar dielectric spacer liner is formed over the planarization dielectric layer, and is patterned to provide an opening over the device contact via structure. An etch stop dielectric liner and a via-level dielectric layer are formed over the planar dielectric spacer liner. An interconnect via cavity may be formed through the via-level dielectric layer by a first anisotropic etch process that may be selective to the etch stop dielectric liner, and may be subsequently extended by a second anisotropic etch process that etches the etch stop dielectric liner. An interconnect via structure may be formed in the interconnect via cavity. A bottom periphery of the interconnect via structure may be self-aligned to the opening in the planar dielectric spacer liner.

Abstract: A semiconductor structure includes a substrate; a conductive pad disposed over the substrate; a passivation disposed over the substrate and covering a portion of the conductive pad; a bump pad disposed over the conductive pad and the passivation; a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; and a dielectric member disposed over the passivation and surrounding the conductive pillar.

Abstract: The present disclosure provides a semiconductor structure, including a bottom terminal, a middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer, a top terminal over the middle terminal and separated from the middle terminal by the high-k dielectric layer, and a silicon nitride layer over the top terminal and directly on the high-k dielectric layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.

Abstract: The present disclosure provides a method for forming a semiconductor structure, including forming a bottom terminal, forming a first middle terminal over the bottom terminal, forming a top terminal over the first middle terminal, forming a first passivation layer over the top terminal, forming a first recess penetrating the first passivation layer and the bottom terminal by using a photomask, forming a dummy layer over the first passivation layer, forming an opening in the dummy layer and over the first recess, forming a conductive material in the first recess and the opening, and removing the dummy layer subsequent to forming the conductive material.

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor.

Abstract: Provided are MIM capacitor and semiconductor structure including MIM capacitor. The MIM capacitor includes a dielectric structure, a bottom electrode on the dielectric structure, a first insulating layer covering the bottom electrode and the dielectric structure, a middle electrode stacked on the bottom electrode, a spacer, a second insulating layer and a top electrode. The middle electrode is separate from the bottom electrode by the first insulating layer therebetween. A bottommost surface of the middle electrode is lower than a top surface of the bottom electrode and higher than a bottom surface of the bottom electrode. The spacer is disposed on the first insulating layer and laterally aside and covers a sidewall of the middle electrode. The second insulating layer covers the middle electrode and the spacer. The top electrode is stacked on the middle electrode and separate from the middle electrode by the second insulating layer therebetween.