Patents by Inventor TUNG-JIUN WU

TUNG-JIUN WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200035595
    Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 30, 2020
    Inventor: TUNG-JIUN WU
  • Publication number: 20190305078
    Abstract: Provided are MIM capacitor and method of manufacturing the same. The MIM capacitor includes a first electrode, a second electrode, a third electrode, a first insulating layer, a second insulating layer, and a first spacer. The first electrode and the third electrode are electrically connected to each other. The first insulating layer is between the first electrode and the second electrode. The second insulating layer is between the second electrode and the third electrode. The first spacer is located between a sidewall of the first electrode and the first insulating layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Jiun Wu, Shun-Yi Lee
  • Patent number: 9711474
    Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Gia-Her Lu, Liang-Chen Lin, Tung-Chin Yeh, Jyun-Lin Wu, Tung-Jiun Wu
  • Publication number: 20160086902
    Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventors: GIA-HER LU, LIANG-CHEN LIN, TUNG-CHIN YEH, JYUN-LIN WU, TUNG-JIUN WU