Patents by Inventor Tung-Liang Shao
Tung-Liang Shao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140183693Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
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Patent number: 8754514Abstract: A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.Type: GrantFiled: August 10, 2011Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hui Yu, Chih-Hang Tung, Tung-Liang Shao, Chen-Hua Yu, Da-Yuan Shih
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Publication number: 20140145307Abstract: A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring.Type: ApplicationFiled: January 17, 2013Publication date: May 29, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai, Hao-Yi Tsai, Tsung-Yuan Yu
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Patent number: 8685798Abstract: Methods for forming through vias in an integrated circuit package are disclosed. A substrate having a first surface is covered with an encapsulation layer of uncured material; the method includes inserting an upper mold tool having a first plurality of pillars into the encapsulation layer to imprint through vias extending to the first surface of the substrate; curing the encapsulation layer and the through vias; removing the upper mold tool from the encapsulation layer; and disposing conductor material within the through vias to make electrical connectors within the through vias. In additional methods, a method for forming an encapsulation layer using an upper and lower mold tool to form through vias and a mold cavity is disclosed.Type: GrantFiled: June 14, 2013Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu, Hao-Yi Tsai, Mirng-Ji Lii, Da-Yuan Shih
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Publication number: 20140087522Abstract: A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Jung Yang, Chang-Pin Huang, Tzuan-Horng Liu, Michael Shou-Ming Tong, Ying-Ju Chen, Tung-Liang Shao, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii
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Patent number: 8618827Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.Type: GrantFiled: October 13, 2010Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Liang Shao, Shih-Wei Liang, Ying-Ju Chen, Ching-Jung Yang, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
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Patent number: 8610267Abstract: A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.Type: GrantFiled: July 21, 2010Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Jung Yang, Chang-Pin Huang, Tzuan-Horng Liu, Michael Shou-Ming Tong, Ying-Ju Chen, Tung-Liang Shao, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii
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Publication number: 20130277840Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.Type: ApplicationFiled: June 17, 2013Publication date: October 24, 2013Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
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Publication number: 20130273698Abstract: Methods for forming through vias in an integrated circuit package are disclosed. A substrate having a first surface is covered with an encapsulation layer of uncured material; the method includes inserting an upper mold tool having a first plurality of pillars into the encapsulation layer to imprint through vias extending to the first surface of the substrate; curing the encapsulation layer and the through vias; removing the upper mold tool from the encapsulation layer; and disposing conductor material within the through vias to make electrical connectors within the through vias. In additional methods, a method for forming an encapsulation layer using an upper and lower mold tool to form through vias and a mold cavity is disclosed.Type: ApplicationFiled: June 14, 2013Publication date: October 17, 2013Inventors: Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu, Hao-Yi Tsai, Mirng-Ji Lii, Da-Yuan Shih
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Patent number: 8531032Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.Type: GrantFiled: September 2, 2011Date of Patent: September 10, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
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Patent number: 8476770Abstract: Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed.Type: GrantFiled: July 7, 2011Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu, Hao-Yi Tsai, Mirng-Ji Lii, Da-Yuan Shih
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Publication number: 20130056871Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.Type: ApplicationFiled: September 2, 2011Publication date: March 7, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
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Publication number: 20130037950Abstract: A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.Type: ApplicationFiled: August 10, 2011Publication date: February 14, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hui Yu, Chih-Hang Tung, Tung-Liang Shao, Chen-Hua Yu, Da-Yuan Shih
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Publication number: 20130009319Abstract: Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed.Type: ApplicationFiled: July 7, 2011Publication date: January 10, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu, Hao-Yi Tsai, Mirng-Ji Lii, Da-Yuan Shih
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Patent number: 8227822Abstract: A light emitting diode apparatus comprises a substrate having a circuit pattern, a reflection layer disposed on the substrate, at least one light emitting element disposed on the reflection layer, a reflector disposed around the at t one light emitting element, a sealing material formed over the at least one light emitting element and a phosphor layer disposed over the sealing material. The light emitting element comprises a conductive portion electrically coupled to the circuit pattern. In one embodiment, a plurality of light emitting elements are linearly arrayed, and a spacer is disposed between every two adjacent light emitting elements.Type: GrantFiled: October 13, 2009Date of Patent: July 24, 2012Assignee: AU Optronics CorporationInventors: Chun Chang Hung, Tung Liang Shao, Falcon Lin
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Publication number: 20120092033Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.Type: ApplicationFiled: October 13, 2010Publication date: April 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tung-Liang Shao, Shih-Wei Liang, Ying-Ju Chen, Ching-Jung Yang, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
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Publication number: 20120018875Abstract: A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.Type: ApplicationFiled: July 21, 2010Publication date: January 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Jung Yang, Chang-Pin Huang, Tzuan-Horng Liu, Michael Shou-Ming Tong, Ying-Ju Chen, Tung-Liang Shao, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii
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Patent number: 7911556Abstract: A backlight module having replaceable lamp module is provided. The backlight module includes a replaceable lamp module, a light-guiding plate, a frame and a positioning and protecting mechanism. The light-guiding plate is disposed over the bottom surface among four sides of the frame, wherein one side of the light-guiding plate and a corresponding side of the frame form a sliding groove. The replaceable lamp module is set in the sliding groove and slidably along the sliding groove. The positioning and protecting mechanism comprises a protecting device set on the replaceable lamp module and a positioning device set on the frame. The protecting device is capable of forming a gap between the replaceable lamp module and the bottom of the sliding groove in order to protect the replaceable lamp module from scraped by the structures of the backlight module while the replaceable lamp module is inserting into the sliding groove.Type: GrantFiled: January 21, 2010Date of Patent: March 22, 2011Assignee: AU Optronics Corp.Inventors: Chi-chun Yang, Tung-liang Shao, Ye-hen Chien
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Patent number: 7821595Abstract: A backlight module includes a frame, an optical element, a bottom plate, a holder, and a light source. The optical elements are located on the frame and a space between the sidewall of the frame and the optical elements. The bottom plate located under the optical elements. The light source is on the holder inserted into the space, The holder is inserted into the space along the direction toward the bottom surface of the bottom plate, and is removed from the space along the opposing direction.Type: GrantFiled: June 2, 2010Date of Patent: October 26, 2010Assignee: Au Optronics CorporationInventors: Therm-Hoo Ke, Ying-Feng Hsu, Chi-Chun Yang, Li-Chuan Yu, Tzu-Yi Liu, Tung-Liang Shao, Tung-I Yen, Shih-Chang Chang
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Publication number: 20100238371Abstract: A backlight module includes a frame, an optical element, a bottom plate, a holder, and a light source. The optical elements are located on the frame and a space between the sidewall of the frame and the optical elements. The bottom plate located under the optical elements. The light source is on the holder inserted into the space, The holder is inserted into the space along the direction toward the bottom surface of the bottom plate, and is removed from the space along the opposing direction.Type: ApplicationFiled: June 2, 2010Publication date: September 23, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Therm-Hoo Ke, Ying-Feng Hsu, Chi-Chun Yang, Li-Chuan YU, Tzu-Yi Liu, Tung-Liang Shao, Tung-I Yen, Shih-Chang Chang