Abstract: Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.

Abstract: A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.

Abstract: A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.

Abstract: A substrate and a method of making thereof are disclosed. The substrate comprises an electrically conductive leadframe, the leadframe having a plurality of lands on a first side of the leadframe with a first recessed portion between the lands, and a plurality of routing leads on an opposing second side of the leadframe with a second recessed portion between the routing leads. The substrate also comprises a first bonding compound filling the first recessed portion. In one embodiment, the substrate also comprises a support material attached to the first bonding compound for holding the leadframe together. In another embodiment, the substrate comprises a second bonding compound filling the second recessed portion.

Abstract: A substrate and a method of making thereof are disclosed. The substrate comprises an electrically conductive leadframe, the leadframe having a plurality of lands on a first side of the leadframe with a first recessed portion between the lands, and a plurality of routing leads on an opposing second side of the leadframe with a second recessed portion between the routing leads. The substrate also comprises a first bonding compound filling the first recessed portion. In one embodiment, the substrate also comprises a support material attached to the first bonding compound for holding the leadframe together. In another embodiment, the substrate comprises a second bonding compound filling the second recessed portion.

Abstract: A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.

Abstract: A substrate for integrated circuit package is disclosed. The substrate comprises an electrically conductive leadframe having a first side and an opposing second side. The substrate has a first bonding compound disposed in a first recessed portion of the first side and a second bonding compound disposed in at least a portion of a second recessed portion of the leadframe, selectively exposing a selected area of the leadframe on the second side. In an exemplary embodiment, the second bonding compound is a photolithographic material. A method of manufacturing a substrate for integrated circuit package is also disclosed.

Abstract: A substrate and a method of making thereof are disclosed. The substrate comprises an electrically conductive leadframe, the leadframe having a plurality of lands on a first side of the leadframe with a first recessed portion between the lands, and a plurality of routing leads on an opposing second side of the leadframe with a second recessed portion between the routing leads. The substrate also comprises a first bonding compound filling the first recessed portion. In one embodiment, the substrate also comprises a support material attached to the first bonding compound for holding the leadframe together. In another embodiment, the substrate comprises a second bonding compound filling the second recessed portion.

Abstract: A substrate for integrated circuit package is disclosed. The substrate comprises an electrically conductive leadframe having a first side and an opposing second side. The substrate has a first bonding compound disposed in a first recessed portion of the first side and a second bonding compound disposed in at least a portion of a second recessed portion of the leadframe, selectively exposing a selected area of the leadframe on the second side. In an exemplary embodiment, the second bonding compound is a photolithographic material. A method of manufacturing a substrate for integrated circuit package is also disclosed.

Abstract: A substrate and a method of making thereof are disclosed. The substrate comprises an electrically conductive leadframe, the leadframe having a plurality of lands on a first side of the leadframe with a first recessed portion between the lands, and a plurality of routing leads on an opposing second side of the leadframe with a second recessed portion between the routing leads. The substrate also comprises a first bonding compound filling the first recessed portion. In one embodiment, the substrate also comprises a support material attached to the first bonding compound for holding the leadframe together. In another embodiment, the substrate comprises a second bonding compound filling the second recessed portion.

Abstract: A semiconductor including a selectively plated lead frame is disclosed. The lead frame contains a die pad and a plurality of lead fingers, where each lead finger is formed with a bonding pad on the center portion of the lead finger by selective plating. The surface area of the lead finger material is increased so the adhesion to molding material is improved. The edges of the lead finger tips are half etched to further increase the surface area of lead finger material. A method of manufacturing the lead frame is also provided.

Abstract: A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.

Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.

Abstract: Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.

Abstract: A semiconductor including a selectively plated lead frame is disclosed. The lead frame contains a die pad and a plurality of lead fingers, where each lead finger is formed with a bonding pad on the center portion of the lead finger by selective plating. The surface area of the lead finger material is increased so the adhesion to molding material is improved. The edges of the lead finger tips are half etched to further increase the surface area of lead finger material. A method of manufacturing the lead frame is also provided.

Abstract: A semiconductor including a selectively plated lead frame is disclosed. The lead frame contains a die pad and a plurality of lead fingers, where each lead finger is formed with a bonding pad on the center portion of the lead finger by selective plating. The surface area of the lead finger material is increased so the adhesion to molding material is improved. The edges of the lead finger tips are half etched to further increase the surface area of lead finger material. A method of manufacturing the lead frame is also provided.

Abstract: In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed.

Abstract: In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed.

Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The leadframe having a spiral inductor etched therein.

Abstract: A semiconductor including a selectively plated lead frame is disclosed. The lead frame contains a die pad and a plurality of lead fingers, where each lead finger is formed with a bonding pad on the center portion of the lead finger by selective plating. The surface area of the lead finger material is increased so the adhesion to molding material is improved. The edges of the lead finger tips are half etched to further increase the surface area of lead finger material. A method of manufacturing the lead frame is also provided.