INTEGRATED CIRCUIT PACKAGE HAVING A CASTELLATED HEATSPREADER
In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed.
Latest GREEN ARROW ASIA LIMITED Patents:
This application is a divisional application of patent application having Ser. No. 12/512,009 filed on Jul. 29, 2009, which claims benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application having Ser. No. 61/185,970 filed on Jun. 10, 2009, the entirety of which is enclosed herewith by reference.
FIELD OF INVENTIONThis invention relates generally to integrated circuit (IC) packaging technology and, in particular to IC packages having enhanced heat dissipation and related methods of manufacture.
BACKGROUND OF INVENTIONIC packaging is one of the final stages involved in the fabrication of IC devices. During IC packaging, one or more IC chips are mounted on a package substrate, connected to electrical contacts, and then coated with an encapsulation material comprising an electrical insulator such as epoxy or silicone molding compound. The resulting structure, commonly known as an “IC package,” may then be mounted onto a printed circuit board (PCB) and/or connected to other electrical components. In most IC packages, the IC chip is completely covered by the encapsulation material, while the electrical contacts are at least partially exposed so that they can be connected to other electrical components.
IC chips generate a great deal of heat during normal operation. As the speed of the IC chips has increased, so too has the amount of heat generated by them. It is desirable to dissipate this heat from an IC package in an efficient manner.
SUMMARY OF INVENTIONThe present invention relates to IC packages having enhanced heat dissipation and related methods of manufacturing. More particularly, in one aspect, the invention features an IC package with an IC chip electrically connected to a substrate and a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip. In some embodiments, the heatspreader may have a castellated texture on a bottom side thereof for enhanced adhesion with the encapsulation material and increased heat dissipation.
In one embodiment, the IC package comprises a leadframe having a first surface and an opposing second surface. A first surface of an IC chip is mounted on the first surface of the leadframe. An encapsulation embeds the first surface of leadframe and a second surface of the IC chip at a first side. A heat sink comprising a base sheet and at least one castellation is disposed on top of the leadframe. The castellation extends from a first surface of the base sheet and they are all embedded in a second side of the encapsulation. A second surface of the base sheet is exposed to the environment.
In another embodiment, the IC package further comprises a central castellation that extends from the first surface of the base sheet. A center of the central castellation is aligned to a center of the IC chip to minimize the distance between the heat sink and the IC chip to improve heat dissipation performance.
In another embodiment of the present invention, the IC package further comprises a metal clip on at least one side that clamps the second surface of the base sheet and the surface opposing that. The metal clip further prevents the second leadframe from detaching and also improves heat dissipation performance of the IC package by directly contacting the PCB when the leadframe is soldered to the PCB, such that heat can be transferred from the heat sink to the PCB so it can be spread away even faster.
According to another aspect of the present invention, a method of manufacturing the IC package as described above is disclosed. The method comprises the steps of etching a leadframe strip to define a leadframe having a first surface and an opposing second surface, mounting a second surface of an IC chip on the first surface of the leadframe, and fixing the leadframe and a heat sink strip in a mold, such that the heat sink strip is disposed in close proximity to the IC chip and a cavity exists therebetween. The cavity is then encapsulated by an encapsulation compound such that the first surface of the leadframe strip and the second surface of the IC chip are embedded in one side of the encapsulation and the heat sink strip is embedded in an opposing side of the encapsulation. The IC package is then singulated from the leadframe strip, the heat sink strip and the encapsulation.
In one embodiment, the method further comprises a step of etching a first surface of the heat sink strip to define at least one castellation.
In another embodiment, the method further comprises a step of attaching a metal clip to at least one side of the IC package.
There are many advantages to the present invention. A heat sink with castellations greatly increases the surface area of contact between the heat sink and the encapsulation. As a result, the adhesion of the heat sink to the encapsulation is increased.
In this invention, a thin layer of encapsulation separates the heat sink from the IC chip, preventing them to be in direct contact. This reduces the chance that the IC chip will be damaged during the fabrication process, and also prevents short circuiting the IC chip and the heat sink. A surface of the heat sink is further exposed to the external environment of the IC package to improve heat dissipation to the environment.
If the castellations are etched from the heat sink strip, the etching process produces undercuts at the side surfaces of the castellations. By being concavely curved, the undercuts further increases the amount of surface area of contact between the heat sink and the encapsulation. The undercuts also provide better interlocking between the heat sink and the encapsulation to further decrease the chance of detaching.
The central castellation is aligned to the IC chip, with a thin layer of encapsulation separating the two. That way, the distance between the two is minimized regardless of the package thickness while still preventing the two to be in direct contact.
Various embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Throughout the specification and claims, the terms “IC chip” and “semiconductor die” are used interchangeably. The same applies to the terms “heatspreader” and “heat sink”.
Referring now to
Referring now to
Referring now to
Having the castellations 110 extending from the base sheet 107 as opposed to the bottom surface being a flat surface greatly improves the adhesion and attachment of the heatspreader 106 to an encapsulation compound which embeds the bottom surface of the heatspreader 106. In this invention, the contact area between the heatspreader 106 and the encapsulation compound is substantially increased over the traditional flat heat sinks. Also, the castellations 110 extending into the encapsulation compound means that the heatspreader 106 is able to withstand a larger shear force from the side as the castellations 110 interlocks with the encapsulation compound in the horizontal plane, while traditional flat heat sinks can only rely on adhesion force to keep the heat sink from moving sideways.
A side view of a castellation 110 is shown in
Referring now to
In thin IC packages, heat generated from the IC chip 104 only needs to travel for a short distance to reach the environment through the base sheet 107. However, as the IC packages get thicker, the distance between the IC chip 104 and the base sheet 107 also increases. If a central castellation 112 is absent, heat will need to travel through a thick layer of encapsulation compound before reaching the base sheet 107. With the central castellation 112, the thickness of the encapsulation compound between the heatspreader 106 and the IC chip 104 can be kept to a minimum. As the central castellation 112 is made of a thermally conductive material with thermal properties superior to the encapsulation compound, heat dissipation performance for the IC package is increased.
Referring now to
The main difference between this embodiment and the one shown in
Having an attached central castellation 112 also makes it easy for the heatspreader 106 to adapt to different IC package thicknesses. In the previous embodiment, in order to keep the layer of encapsulation between the IC chip 104 and the central castellation 112 to be thin, heatspreaders 106 etched from heatspreader strips 108 will need to be of different thicknesses. In this embodiment, the same configuration and thickness of base sheet 107 and the castellations 110 can be used for IC package of all thicknesses, as the thickness of the central castellation 112 can be changed independently to the base sheet 107 to adapt to different IC package thicknesses.
Referring now to
At step S306 as shown in
The IC package 118 as shown in
Referring now to
The metal clip 120 decreases the likelihood of separation between the heatspreader 106 and the leadframe 102. Additionally, the metal clip 120 increases the heat dissipation from the heatspreader 106 by thermally coupling the heatspreader 106 to a surface below the IC package 118 such as, for example, a PCB. In one embodiment, the metal clip 120 contacts the PCB when the leadframe 102 is bonded or soldered to the PCB. In another embodiment, the metal 120 is in close proximity to the PCB. The metal clip 120 also increases the surface area that heat can be dissipated from, so heat dissipation performance is further improved.
To produce the integrated circuit package as shown in
Although various embodiments of the method and system of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth herein.
For example, the top surface of the base sheet 107 is flat or untextured in the embodiments described. However, it is obvious that the top surface can also be partially etched or otherwise plated with additional material to form a patterned surface to further increase the surface area of the heatspreader 106. In an embodiment, the mold follows the contour of the top surface of the base sheet 107 such that encapsulation compound 114 will not be injected between the upper mold half and the top surface of the base sheet 107.
The embodiments above described that the castellations can be formed by either etching and layering. It is clear to a person skilled in the art that both methods can be used in the same heatspreader if they so wish.
The IC package 118 as shown in
The side surfaces of the castellations 110 are shown as concave in the embodiment, but it could be convex or having a sharp corner as long as the shape has a larger surface area than flat surface while improves interlocking.
Claims
1. A method for fabricating an integrated circuit package, comprising the steps of:
- a) etching a leadframe strip to define a leadframe having a first surface and an opposing second surface;
- b) attaching a semiconductor die having a first surface and an opposing second surface to said leadframe by mounting said first surface of said semiconductor die on said first surface of said leadframe;
- c) fixing said leadframe strip and a heat sink strip to a mold, said heat sink strip having a first surface facing said semiconductor die and an opposing second surface, wherein said heat sink strip is disposed in close proximity to said semiconductor die and a cavity exists between said heat sink strip and said leadframe strip when fixed to said mold;
- d) encapsulating said cavity with an encapsulation compound, wherein said first surface of said leadframe strip, said second surface of said semiconductor die, and said first surface of said heat sink strip are embedded in said encapsulation compound, such that a layer of encapsulation compound separates said heat sink strip from said semiconductor die and said leadframe strip;
- e) singulating said integrated circuit package from said leadframe, said heat sink strip and said encapsulation compound.
2. The method according to claim 1, further comprising the step of etching said first surface of said heat sink strip to define at least one castellation extending from said first surface of said heat sink strip.
3. The method according to claim 2, wherein said etching step produces an undercut in at least one surface of said castellation.
4. The method according to claim 1, further comprising the step of attaching at least one castellation on said first surface of said heat sink strip.
5. The method according to claim 1, further comprising the step of etching said first surface of said heat sink strip to define a central castellation extending from said first surface of said heat sink strip, a center of said central castellation aligned to a center of said semiconductor die.
6. The method according to claim 5, wherein said etching step produces an undercut in at least one surface of said central castellation.
7. The method according to claim 1, further comprising the step of attaching a central castellation on said first surface of said heat sink strip.
8. The method according to claim 1, further comprising attaching a metal clip to at least one side of said integrated circuit package, said metal clip contacts said second surface of said heat sink strip and a surface of said integrated circuit package opposing said second surface of said heat sink strip.
Type: Application
Filed: Dec 21, 2010
Publication Date: Apr 21, 2011
Applicant: GREEN ARROW ASIA LIMITED (Tsuen Wan)
Inventor: Tung Lok LI (Hong Kong)
Application Number: 12/975,310
International Classification: H01L 21/50 (20060101);