Patents by Inventor Tung-Wen CHENG

Tung-Wen CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240271287
    Abstract: The present disclosure provides a gas sensor. The gas sensor includes a substrate, an insulating layer over the substrate, a conductor layer over and in contact with a top surface of the substrate, and a gas sensing film. The conductor layer includes a conductive pattern having a plurality of openings, and the conductive pattern is embedded in the insulating layer. The gas sensing film is formed over a portion of the conductive pattern.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 15, 2024
    Inventors: MING-TA LEI, CHIA-HUA CHU, HSIN-CHIH CHIANG, TUNG-TSUN CHEN, CHUN-WEN CHENG
  • Publication number: 20230352592
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.
    Type: Application
    Filed: June 21, 2023
    Publication date: November 2, 2023
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang, Chang-Yin Chen
  • Patent number: 11721762
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang, Chang-Yin Chen
  • Patent number: 11705519
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
  • Publication number: 20230146994
    Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.
    Type: Application
    Filed: January 3, 2023
    Publication date: May 11, 2023
    Inventors: CHE-CHENG CHANG, TUNG-WEN CHENG, ZHE-HAO ZHANG, YUNG JUNG CHANG
  • Patent number: 11631748
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen Cheng, Zhe-Hao Zhang
  • Patent number: 11594534
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
  • Patent number: 11594635
    Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Yung Jung Chang
  • Patent number: 11545572
    Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Yung Jung Chang
  • Publication number: 20220375796
    Abstract: In a method for manufacturing a semiconductor device, a fin structure is formed over a substrate, an isolation insulating layer is formed over the substrate such that an upper portion of the fin structure protrudes from the isolation insulating layer, a first dielectric layer is formed on the upper portion of the fin structure, a cover layer is formed on the first dielectric layer, the cover layer is partially removed from an upper part of the upper portion of the fin structure with the first dielectric layer, the first dielectric layer is removed from the upper part of the upper portion of the fin structure, a second dielectric layer is formed on the upper part of the upper portion of the fin structure, and a gate electrode is formed on the second dielectric layer and the first dielectric layer disposed on an lower part of the upper portion of the fin structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 24, 2022
    Inventors: Jen-Chun CHOU, Tung-Wen CHENG
  • Patent number: 11424165
    Abstract: In a method for manufacturing a semiconductor device, a fin structure is formed over a substrate, an isolation insulating layer is formed over the substrate such that an upper portion of the fin structure protrudes from the isolation insulating layer, a first dielectric layer is formed on the upper portion of the fin structure, a cover layer is formed on the first dielectric layer, the cover layer is partially removed from an upper part of the upper portion of the fin structure with the first dielectric layer, the first dielectric layer is removed from the upper part of the upper portion of the fin structure, a second dielectric layer is formed on the upper part of the upper portion of the fin structure, and a gate electrode is formed on the second dielectric layer and the first dielectric layer disposed on an lower part of the upper portion of the fin structure.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Chun Chou, Tung-Wen Cheng
  • Patent number: 11342458
    Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin
  • Patent number: 11158744
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
  • Publication number: 20210313468
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao ZHANG, Bo-Feng YOUNG
  • Patent number: 11120974
    Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Tung-Wen Cheng, Che-Cheng Chang, Jr-Jung Lin, Chih-Han Lin
  • Publication number: 20210280581
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.
    Type: Application
    Filed: May 6, 2021
    Publication date: September 9, 2021
    Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
  • Patent number: 11043593
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
  • Patent number: 11018259
    Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lo, Tung-Wen Cheng, Chia-Ling Chan, Mu-Tsang Lin
  • Patent number: 11004845
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
  • Publication number: 20210118742
    Abstract: In a method for manufacturing a semiconductor device, a fin structure is formed over a substrate, an isolation insulating layer is formed over the substrate such that an upper portion of the fin structure protrudes from the isolation insulating layer, a first dielectric layer is formed on the upper portion of the fin structure, a cover layer is formed on the first dielectric layer, the cover layer is partially removed from an upper part of the upper portion of the fin structure with the first dielectric layer, the first dielectric layer is removed from the upper part of the upper portion of the fin structure, a second dielectric layer is formed on the upper part of the upper portion of the fin structure, and a gate electrode is formed on the second dielectric layer and the first dielectric layer disposed on an lower part of the upper portion of the fin structure.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 22, 2021
    Inventors: Jen-Chun CHOU, Tung-Wen CHENG