Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

Abstract: A method for forming a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

Abstract: A semiconductor device includes a fin-like structure extending along a first axis; a first source/drain feature disposed at a first end portion of the fin-like structure; and a constraint layer disposed at a first side of the first end portion of the fin-like structure, wherein the first source/drain feature comprises a first portion, disposed at the first side, the first portion comprising a shorter extended width along a second axis, and a second portion, disposed at a second side that is opposite to the first side, the second portion comprising a longer extended width along the second axis.

Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

Abstract: A semiconductor device includes a fin-like structure extending along a first axis; a first source/drain feature disposed at a first end portion of the fin-like structure; and a constraint layer disposed at a first side of the first end portion of the fin-like structure, wherein the first source/drain feature comprises a first portion, disposed at the first side, the first portion comprising a shorter extended width along a second axis, and a second portion, disposed at a second side that is opposite to the first side, the second portion comprising a longer extended width along the second axis.

Abstract: A transistor includes a semiconductive fin having a channel portion, a gate stack over the channel portion of the semiconductive fin, source and drain structures on opposite sides of the gate stack and adjoining the semiconductive fin, and a sidewall structure extending along sidewalls of a body portion of the source structure. The source structure has a curved top, and the source structure has a top portion protruding over a top of the sidewall structure.

Abstract: A method for manufacturing a porous membrane includes: mixing silicon carbide powders and a coagulant to form a first mixture; adding a sintering aid to the first mixture to form a second mixture; compressing the second mixture; and sintering the compressed second mixture. More particularly, the coagulant is in an amount of 1% to 3% by weight of the silicon carbide powders and the sintering aid is in an amount of 10% by weight of the first mixture.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.