Patents by Inventor Tung

Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9130375
    Abstract: The disclosure provides a charger including a base and a charging circuit. The base includes a coupling portion for detachably coupling with one of multiple supporting stands. Each of the supporting stands has a supporting container with different standards. The coupling portion has a coupling surface. The coupling surface is used for supporting one of the supporting stands. The charging circuit is disposed in the base and the charging circuit has a first electrical connector. The first electrical connector protrudes from the coupling surface. When the coupling portion is coupled with the supporting stand, a portion of the first electrical connector is disposed in the supporting container.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 8, 2015
    Assignee: CIPHERLAB CO., LTD.
    Inventors: Chi-Ming Yeh, Tung-Han Lee, Ming-Huang Lee, Wang-Hung Chiang
  • Patent number: 9130058
    Abstract: A device includes a plurality of intra-device insulation regions having a first height; and a plurality of semiconductor fins horizontally spaced apart from each other by the plurality of intra-device insulation regions. A portion of the plurality of semiconductor fins is disposed above the plurality of intra-device insulation regions. The device further includes a first inter-device insulation region and a second inter-device insulation region with the plurality of semiconductor fins disposed therebetween. The first and the second inter-device insulation regions have a second height greater than the first height.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
  • Patent number: 9127426
    Abstract: A securing and waterproof mechanism of a floodgate apparatus includes a pillar, a water retaining gate, a pair of retaining bases and a securing member. The pillar has a retaining groove for receiving the water retaining gate. The retaining bases are attached to two opposite sides of the pillar. Each retaining base has at least one vertical channel. The securing member has two hook portions at one side. Each hook portion has a horizontal bar and a vertical bar extending upward from a distal end of the horizontal bar. Under this arrangement, the vertical bar of each hook portion is fitted in the vertical channel of the respective retaining base to prevent the securing member from sliding horizontally off the respective retaining base.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: September 8, 2015
    Inventor: Tung-Lin Wu
  • Patent number: 9130328
    Abstract: A RF pass-through connector comprises at least a spring-loaded terminal comprised of a rod member and a sleeve member resiliently telescopically formed in a housing and adapted to be correspondingly contacted with a signal terminal formed in a socket and a receptacle cavity in the socket to be electrically connected with a grounding loop formed in a circuit board fixed in an electronic device, whereby upon a connection of the RF pass-through connector with the socket of the electronic device, a reliable, stable and efficient signal communication or transmission may be obtained through the terminals.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: September 8, 2015
    Assignee: Insert Enterprise Co., Ltd.
    Inventors: Tung-Liang Huang, Sung-Wen Chen
  • Publication number: 20150248515
    Abstract: Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 3, 2015
    Inventors: Xijiang Lin, Ting-Pu Tai, Wu-Tung Cheng, Takeo Kobayashi
  • Publication number: 20150247284
    Abstract: Disclosed are processes for applying dyes, optional stain blocker and anti-soil compositions on single BCF yarns during rewinding, prior to twisting, weaving, knitting or tufting. The processes forego the need to dye and otherwise treat carpets and other textiles made from the BCF yarn using current methods. Also disclosed are systems, BCF yarns, and carpets made from the BCF yarn treated by the disclosed process.
    Type: Application
    Filed: September 18, 2013
    Publication date: September 3, 2015
    Applicant: INVISTA NORTH AMERICA S.A.R.L.
    Inventors: Wae-Hai Tung, Ronnie Rittenhouse
  • Patent number: 9122835
    Abstract: A method for generating a layout pattern of integrated circuit (IC) is provided. First, feature patterns are provided to a computer system and dummy pad patterns are generated in a space among the feature patterns. The layout pattern is then split into first feature patterns and second feature patterns. The dimensions of the first feature patterns are less than the dimensions of the second feature patterns. Afterwards, the dummy pad patterns are combined with the second features pattern to form a combined pattern. Then, mandrel patterns are generated in a space between the first feature patterns and the geometric patterns are generated according to the positions of the first feature patterns. Finally, the combined pattern, the mandrel patterns, and the geometric patterns are respectively outputted to form a first, a second, and a third photomasks.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: September 1, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 9125323
    Abstract: A rear end of a main body of a rack body with an airflow blocking mechanism is pivotally coupled to a blocking sheet, and the blocking sheet is adjusted to be levelly or erectly disposed conveniently; the position change of the blocking sheet is relied on to control air to flow into a rack body or not to allow the rack body installed with no electronic device in the same computer housing to have an airflow blocking function to avoid decreasing air amount flowing through other rack bodies installed with an electronic device so as to elevate the electronic device cooling efficiency.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: September 1, 2015
    Assignee: WISTRON CORPORATION
    Inventors: Tung-Ping Lee, Ming-Hui Kao
  • Patent number: 9123177
    Abstract: A three dimensional processing circuit and processing method is disclosed. In the present invention, a key depth is obtained to change an OSD location by analyzing the key image information in the 3D image. Therefore, the disadvantages of the conventional 3D processing circuit and processing method are fixed so as to decrease fatigue of user's eyes.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: September 1, 2015
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Hsu-Jung Tung, Chia-Wei Yu
  • Patent number: 9122908
    Abstract: Disclosed herein is a method for counting the number of the targets using the layer scanning method. The steps of this method includes constructing a background frame, filtering the noise of foreground frame and classifying the targets, and screening the area of targets based on layer scanning to calculate the number of targets by determining the highest positions of the respective targets. In addition, the dynamic numbers of targets are calculated using algorithm. Accordingly, the present invention is beneficial in automatically, effectively and precisely calculating the number of the targets in/out a specific area, achieving the flow control for targets and reducing artificial error upon calculation.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: September 1, 2015
    Assignee: National Chiao Tung University
    Inventors: Daw-Tung Lin, Dong-Han Jhuang
  • Patent number: 9123617
    Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Hsun Wan, Yi-Shin Chu, Szu-Ying Chen, Pao-Tung Chen, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 9122669
    Abstract: A method and system includes a server that provides a business management service to multiple independent customers. A template repository provides predefined templates, and a configuration storage stores customer changes to the predefined templates that represent customized templates. A user interface facilitates selection of customized templates as a function of scope of work for fine tuning.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: September 1, 2015
    Assignee: SAP SE
    Inventors: Hilmar Demant, Frank Schertel, Johannes Bechtold, Olaf Meincke, Peter Eberlein, Thierry Tung, Eckhard Farrenkopf, Cheng Wang, Ramesh B. G., Juergen Sattler
  • Patent number: 9121646
    Abstract: A heat-dissipation unit coated with oxidation-resistant nano thin film includes a metal main body having a heat-absorbing portion and a heat-dissipating portion, both of which are coated with at least a nano metal compound thin film. To form the nano metal compound thin film on the heat-dissipation unit, first form at least a nano compound coating on an outer surface of the heat-dissipation unit, and then supply a reduction gas into a high-temperature environment to perform a heat treatment and a reduction process on the heat-dissipation unit and the nano compound coating thereof, and finally, a nano metal compound thin film is formed on the surface of the heat-dissipation unit after completion of the heat treatment and the reduction process. With the nano metal compound thin film, the heat-dissipation unit is protected against formation of oxide on its surface and accordingly against occurrence of increased thermal resistance thereof.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 1, 2015
    Assignee: Asia Vital Components Co., Ltd.
    Inventor: Ying-Tung Chen
  • Patent number: 9122827
    Abstract: A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Tsun Chen, Yung-Chow Peng, Jui-Cheng Huang
  • Publication number: 20150241789
    Abstract: An immersion lithography apparatus includes a lens system, an immersion hood, a wafer stage, an inspection system and a cleaning fluid supplier. The lens system is configured to project a pattern onto a wafer. The immersion hood is configured to confine an immersion fluid between the lens system and the wafer, and includes a peripheral hole configured to suck up the immersion fluid. The wafer stage is configured to position the wafer under the lens system. The inspection system is configured to detect whether there is contamination in the peripheral hole. The cleaning fluid supplier is coupled to the inspection system and configured to supply a cleaning fluid through the peripheral hole to remove the contamination, in which the inspection system and the cleaning fluid supplier are coupled to the wafer stage.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Li WU, Heng-Hsin LIU, Jui-Chun PENG
  • Publication number: 20150244465
    Abstract: An optical signal emitter includes a transmitting lens; a lens supporting portion, extending from an edge of the transmitting lens to defined a containing space surrounded by the transmitting lens and the lens supporting portion; a lens carrier, for carrying the transmitting lens and the lens supporting portion, wherein a coupling surface is defined on the lens carrier and at least a part of the lens supporting portion is coplanar with the lens carrier with respect to the coupling surface; a light transmitter, disposed in the containing space and coaxially with the transmitting lens, so as to define an light transmission path for light passing through coupling surface by an alignment between the light transmitter and the transmitting lens; at least one engagement portion, disposed on the coupling surface; at least one magnet, disposed on the lens carrier.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 27, 2015
    Inventors: Hui-Tsuo Chou, Tung Lou Lin, Hsieh Yi Chou
  • Publication number: 20150243763
    Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin, Wei-Li Chen
  • Publication number: 20150243659
    Abstract: A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: YU-LIEN HUANG, CHI-KANG LIU, YUNG-TA LI, CHUN-HSIANG FAN, TUNG-YING LEE, Clement HSING-JEN WANN
  • Publication number: 20150239135
    Abstract: An out the front assisted knife has a casing, a blade and a secondary pusher. The casing has a secondary channel hole formed through the casing, extending axially, and disposed away from an axial inner end of the casing. The secondary pusher is axially movably mounted in the casing, protrudes out of the secondary channel hole of the casing, and axially abuts against the inner end of the blade. The secondary pusher is disposed away from the axial inner end of the casing, such that the user's hand holds at least half of the casing when pressing the thumb on the secondary pusher to extend the blade. Therefore, the user can hold the knife by the center of gravity of the knife, and thus can stably and conveniently operate the knife, thereby preventing the knife from dropping accidentally.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 27, 2015
    Inventors: Ji-Tung CHU, Jiun-Yu CHU
  • Publication number: 20150244563
    Abstract: The differentiated service-based graceful degradation layer (DSGDL) allows cloud-based architectures to operate through and recover from periods of limited capability. The DSGDL protects and continues serving higher priority requests with the best possible response even as the underlying cloud-based services deteriorate. The DSGDL offloads lower priority requests to lower-grade secondary capability that can be dynamically provisioned in order to reserve the best capability for maintaining high priority service (e.g., by re-directing lower priority requests to a slightly out-of-date cached dataset, and reserve the primary consistent database for higher priority requests). The DSGDL 1) implements an overlay network over existing cloud services to route and enforce priority requests, and 2) provisions on-demand computing nodes and sites to provide secondary capability for service requests as needed.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 27, 2015
    Inventors: Teresa Tung, Shaw-Yi Chaw, Qing Xie, Qian Zhu