Abstract: Some implementations described herein include a semiconductor device including a thin film resistor structure and techniques for forming the thin film resistor structure. Techniques described herein include forming a layer of a resistive material using a dual-component physical vapor deposition process and forming contact structures on the layer of resistive material by directly patterning a layer of conductive material on the layer of the resistive material. The techniques further include oxidizing a surface of the layer of the resistive material between the contact structures.

Abstract: Some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. A material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. Furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

Abstract: Resistors and method of forming the same are provided. A device structure according to the present disclosure includes a substrate, a first intermetal dielectric (IMD) layer over the substrate, a resistor that includes a first resistor layer over the first IMD layer, a second resistor layer over the first resistor layer, and a third resistor layer over the second resistor layer, a second IMD layer over the first IMD layer and the resistor, a first contact via extending through the second IMD layer and the third resistor layer and terminating in the first resistor layer, and a second contact via extending through the second IMD layer and the third resistor layer and terminating in the first resistor layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

Abstract: Some implementations described herein include a semiconductor device including a semiconductor resistor structure having and techniques for forming the semiconductor resistor structure. The techniques include forming a layer of a silicon chromium material having different silicon/chromium ratios within the layer (e.g., a graded resistive layer) as part of forming the semiconductor resistor structure. The graded resistive layer may compensate for semiconductor manufacturing processes (e.g., etching, oxidation, thermal annealing) that may lead to film damage, thinning, crystallization, or composition drift of the graded resistive layer to enlarge process windows for fabricating the semiconductor resistor structure. The enlarged process window may improve a performance of the semiconductor resistor structure (e.g., a resistance and/or an impedance uniformity) relative to another semiconductor resistor structure fabricated using a uniform layer of a silicon chromium material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.