Patents by Inventor Tuo-Hsin Chien

Tuo-Hsin Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9373627
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
  • Publication number: 20150140752
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 21, 2015
    Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
  • Patent number: 8952442
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
  • Publication number: 20140308798
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
  • Patent number: 8772854
    Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
  • Publication number: 20130256772
    Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 3, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
  • Patent number: 7923787
    Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: April 12, 2011
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-Yung Yang
  • Patent number: 7858466
    Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: December 28, 2010
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
  • Patent number: 7847365
    Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: December 7, 2010
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-yung Yang
  • Patent number: 7615826
    Abstract: An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit function and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: November 10, 2009
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu G. Lin, Ta-yung Yang
  • Publication number: 20090050962
    Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.
    Type: Application
    Filed: October 14, 2005
    Publication date: February 26, 2009
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-yung Yang
  • Publication number: 20080290410
    Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.
    Type: Application
    Filed: October 14, 2005
    Publication date: November 27, 2008
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-yung Yang
  • Patent number: 7417287
    Abstract: An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: August 26, 2008
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
  • Patent number: 7355250
    Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: April 8, 2008
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
  • Patent number: 7285837
    Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.
    Type: Grant
    Filed: January 17, 2005
    Date of Patent: October 23, 2007
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-yu G. Lin, Ta-yung Yang
  • Publication number: 20070178648
    Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
    Type: Application
    Filed: March 6, 2007
    Publication date: August 2, 2007
    Applicant: SYSTEM GENERAL CORP.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien
  • Publication number: 20070117328
    Abstract: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region to respective well of rim core regions of the vertical transistor, the present invention realizes a stable breakdown voltage with short length of the field region. Therefore, the device area and the manufacturing cost can be reduced.
    Type: Application
    Filed: January 11, 2007
    Publication date: May 24, 2007
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-yu Lin, Ta-yung Yang
  • Publication number: 20070096255
    Abstract: A high resistance CMOS resistor with a relatively small die size is provided. The CMOS resistor includes a p-field region disposed in a n-well of a substrate and a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well. The pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor. The CMOS resistor according to the present invention has a resistance of, for example, 10 k?-20 k? per square.
    Type: Application
    Filed: December 6, 2006
    Publication date: May 3, 2007
    Applicant: SYSTEM GENERAL CORP.
    Inventors: CHIH-FENG HUANG, TUO-HSIN CHIEN
  • Patent number: 7205201
    Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: April 17, 2007
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
  • Publication number: 20070052030
    Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 8, 2007
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien