Patents by Inventor Tushar R. Gheewala

Tushar R. Gheewala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4392148
    Abstract: In superconductive circuitry including a superconducting ground plane, a magnetic flux trapping moat is provided which surrounds a superconductive device. The moat is preferably a cut through the superconducting ground plane which extends along a perimeter surrounding the superconducting device, the moat being continuous except for small regions where there is no cut. The small regions serve as current carrying portions to link the ground plane within the moat to the rest of the ground plane outside of the moat. The moat is a flux pinning center so that magnetic flux does not enter the ground plane region located near the superconducting device. In a Josephson circuit, the Josephson tunnel devices are especially sensitive to trapped magnetic flux in the ground plane, and the provision of a moat around each of the devices prevents flux from moving into the ground plane areas near the devices and becoming trapped therein.
    Type: Grant
    Filed: December 31, 1980
    Date of Patent: July 5, 1983
    Assignee: International Business Machines Corporation
    Inventors: Wen H. Chang, Tushar R. Gheewala, Erik P. Harris
  • Patent number: 4365317
    Abstract: This superconductive latch circuit uses superconductive switching devices and can be powered by the same phase of AC power used to power other circuits with which the latch is used. The latch is comprised of a storage loop including a superconductive switch and an inductor. It is also comprised of another superconductive switch through which an AC gate current can flow and whose state determines whether or not the AC current is delivered to the superconductive storage loop. Information is stored in the loop as the presence and absence of a circulating current of either polarity. In a variation of this latch, an output of the sense circuit which detects the state of the storage loop if fed back as a control signal to the superconductive switch in the storage loop and also as one input to an AND gate to which a SET signal is also applied. AC power is switched to the storage loop when both inputs to the AND circuit are simultaneously present.
    Type: Grant
    Filed: August 6, 1980
    Date of Patent: December 21, 1982
    Assignee: International Business Machines Corporation
    Inventor: Tushar R. Gheewala
  • Patent number: 4313066
    Abstract: Direct coupled, nonlinear injection logic circuits having high gain, good isolation between input and output, the capability of parallel fan-in and fan-out, and which do not require a large area. These circuits are comprised of a first stage that isolates the input from the output and other stages which can be used for additional gain, or for building logic circits, such as AND, and DOT-OR. The first stage isolation is a parallel network comprised of two circuits, each circuit of which includes a series connection of resistor-Josephson tunnelling device. A gate current I.sub.g flows through each Josephson device when the devices are in their zero voltage states. An input current I.sub.c is injected into one of the parallel circuits while an output is taken from the other parallel circuit. When an input current is injected, one of the Josephson devices is switched to the nonzero voltage state, which then causes a greater amount of gate current I.sub.
    Type: Grant
    Filed: August 20, 1979
    Date of Patent: January 26, 1982
    Assignee: International Business Machines Corporation
    Inventor: Tushar R. Gheewala