Abstract: Phase change memories may be made with relatively small pore sizes using electron beam lithography. An electrode may be covered with a relatively thin insulator, which may be patterned using direct write electron beam lithography.

Abstract: A programmable resistance memory element having a conductive layer as an electrode. The conductive layer and memory material may have a small area of contact. In one embodiment, the conductive layer may be cup-shaped. In one embodiment, the memory element may include a chalcogenide material.

Abstract: A chalcongenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.

Abstract: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

Abstract: A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

Abstract: A method of making an electrically programmable memory element, comprising: providing a conductive sidewall spacer; and forming a phase-change material in electrical communication with said conductive sidewall spacer.

Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

Abstract: A vertical elevated pore structure for a phase change memory may include a pore with a lower electrode beneath the pore contacting the phase change material in the pore. The lower electrode may be made up of a higher resistivity lower electrode and a lower resistivity lower electrode underneath the higher resistivity lower electrode. As a result, more uniform heating of the phase change material may be achieved in some embodiments and better contact may be made in some cases.

Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

Abstract: A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or threshold switching material between the conductive lines. The matrix array may be used in a programmable logic device.

Abstract: A planarized surface may be formed by initially forming an aperture through an insulating layer. The insulating layer and its aperture may be conformally coated with a conductive material that ultimately acts as a planarization stop. The conductive material may then be covered with another insulator that fills the remainder of the aperture. Thereafter, the structure may be planarized down to the conductive layer that acts as a planarization stop.

Abstract: A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Abstract: A method of testing a programmable resistance memory element. The method comprises applying a plurality of reset pulses to the memory element. Each of the reset pulses having an energy which is greater than the minimum energy needed program the memory element from its set state to its reset state.

Abstract: A vertical elevated pore structure for a phase change memory may include a pore with a lower electrode beneath the pore contacting the phase change material in the pore. The lower electrode may be made up of a higher resistivity lower electrode and a lower resistivity lower electrode underneath the higher resistivity lower electrode. As a result, more uniform heating of the phase change material may be achieved in some embodiments and better contact may be made in some cases.

Abstract: A processor-based system may use a volatile memory with a shadow phase change memory. The shadow phase change memory may be directly coupled to the controller. The controller may also be coupled to the volatile memory which, in turn, may, in some embodiments, be directly coupled to the phase change memory. In a standby mode, the volatile memory may be powered down. In some embodiments, faster speeds may be achieved with lower power consumption and less risk of data loss in the case of a crash or other system failure.

Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havin

Abstract: A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor.

Abstract: A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.