Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havin

Abstract: A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on the chip; storing information about said electronic circuit in the phase-change memory. A method of operating an optical display.

Abstract: An integrated circuit chip, comprising: an electronic device; and a phase-change memory storing information of said electronic device. A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on said chip; storing information about said electronic circuit in said phase-change memory.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A programmable resistance memory element having a conductive layer as an electrode. The conductive layer and memory material may have a small area of contact. In one embodiment, the conductive layer may be cup-shaped. In one embodiment, the memory element may include a chalcogenide material.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A memory element comprising a volume of phase change memory material; and first and second contact for supplying an electrical signal to the memory material, wherein the first contact comprises a conductive sidewall spacer. Alternately, the first contact may comprise a contact layer having an edge adjacent to the memory material.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, the quantity of programmable material is minimized, and the programmable material that is reprogrammed from an amorphous to a crystalline state, and vice versa, is localized on a contact. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. A spacer is formed within the opening and a programmable material is formed within the opening such that the spacer reduces the programmable material on the contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through a dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.

Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

Abstract: An electrically programmable memory element comprising a programmable resistance memory material. In one embodiment, the memory element has a cup-shaped electrical contact. A portion of the rim of the electrical contact is recessed below another portion of the rim.

Abstract: An electrically operated programmable resistance memory element having a conductive layer as an electrical contact. The conductive layer has a raised portion extending from an edge of the layer to an end adjacent the memory material.

Abstract: An amplifier powered by a selectively engageable voltage source and a method for operating the amplifier. The amplifier includes first and second electrodes for receiving an input signal to be amplified. The first and second electrodes are adapted to be respectively connected to coupling capacitors. The amplifier also includes a differential amplifier having inputs respectively connected to the first and second electrodes, and having an output. The amplifier additionally includes selectively engageable resistances coupled between the voltage source and respective inputs of the differential amplifier and defining, with the coupling capacitors, the high pass characteristics of the circuit. The amplifier further includes second selectively engageable resistances coupled between the voltage source and respective inputs of the differential amplifier.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

Abstract: A memory may have access devices formed using a chalcogenide material. The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being accessed. In the case of phase change memory elements, the snapback voltage may be less than the threshold voltage of the phase change memory element.

Abstract: A method of making an electrically operated programmable resistance memory element. A sidewall spacer is used as a mask to form a raised portion of a conductive layer. A programmable resistance material is formed in electrical contact with the raised portion.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. The resistivity of the contact is modified by at least one of implanting ions into the contact, depositing a material on the contact, and treating the contact with plasma. In an aspect, a spacer is formed within the opening and programmable material is formed within the opening and on the modified contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

Abstract: A method of operating a electrically programmable phase-change memory element. The method includes the step of applying an electrical signal to memory element which is sufficient to return the memory element to its pre-drift resistance state.