Abstract: Some embodiments include a delay locked circuit having multiple paths. A first path measures a timing of a first clock signal during a measurement. A second path generates a second clock signal based on the first clock signal. The delay locked circuit periodically performs the measurement to adjust a timing relationship between the first and second clock signals. The time interval between one measurement and the next measurement is unequal to the cycle time of the first clock signal. Additional embodiments are disclosed.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed signal, a second delayed signal, and a third delayed signal by delaying a clock reference signal with various time delays of a coarse delay line and local coarse delay units. This method embodiment also includes generating a clock output signal based on the first delayed signal, the second delayed signal, or the third delayed signal, depending on a phase difference between the clock reference signal and the clock output signal.

Abstract: A clock synchronization circuit (200, FIG. 2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an external clock signal (220) and a feedback signal (222) to evaluate the jitter present in the external clock signal. When the jitter falls within an acceptable range, the circuit operates in DLL mode. In DLL mode, the external clock signal is provided to the delay line, and the delayed external signal is output (224) from the circuit. If the jitter falls outside the acceptable range and the circuit is locked, the circuit is switched to PLL mode. In PLL mode, a clock signal based on the feedback signal is provided to the delay line, and the delayed feedback signal is output from the circuit. The PLL mode is only allowed to operate briefly before switching the circuit back into DLL mode.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path generates an internal signal based on the external signal. The delay locked circuit periodically performs the measurement to keep the external and internal signals synchronized. The time interval between one measurement and the next measurement is unequal to the cycle time of the external signal.

Abstract: The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system includes input, output, and data storage devices, a processor coupled to the devices, a memory device coupled to the processor, and a configuration circuit interposed between the processor and the memory device to selectively couple lines in the address, control and data busses of the processor to lines in the address, control and data busses of the memory device. In another embodiment, a memory device includes an array coupleable to one or more busses of an external device and a configuration circuit between the array and the busses of the external device to selectively couple the busses to the memory cell array. In a particular embodiment, the configuration circuit includes one or more bi-stable relays, such as Micro-Electrical-Mechanical System (MEMS) relays.

Abstract: The present invention provides apparatus and methods relating to delay circuits. An electronic system includes a deskewing circuit configured to measure a delay and generate a synchronized signal according to the measured delay. The deskewing circuit may configured to detect an overflow condition and respond accordingly, for example by asserting an overflow signal. Further, the deskewing circuit may be additionally or alternatively configured to detect successful measurement of the delay and respond, for example by executing a power saving and/or noise reducing procedure.

Abstract: Methods and apparatuses for testing image sensors are disclosed. Desirable apparatuses of the present invention include image sensor testing devices comprising a digital light projection system capable of projecting static or dynamic images onto an image sensing device under test and an image sensor signal detection means for analyzing the output of said image sensing device under test. The digital light projection system comprises a light source, collimating optics, a digital micromirror device, and focusing optics. Other desirable methods and apparatuses of the present invention include image sensor testing devices employing a digital light projection system capable of simultaneously testing a plurality of image sensors. According to the present invention, the light source is calibrated and converted to a desired test image by the digital micromirror device. The test image is then focused onto an image sensor, the output of which is read by a detector and correlated with the input digital test image.

Abstract: A method and apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements may be implemented to provide uniformity in the access time through a range of conditions, such as drain voltages and temperatures.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The pulse generator is configured to receive a delay clock signal generated based on the input clock signal and generate a pulse, the pulse having a falling edge corresponding to a rising edge of the delay clock signal. The measure delay array is coupled to the pulse generator to receive the pulse. The measure circuit is configured to determine a position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal. The forward delay array is configured to receive the input clock signal and delay the input clock signal based on the position determined by the measure circuit to generate the output clock signal. A method for synchronizing an output clock signal with an input clock signal includes receiving a delay clock signal generated based on the input clock signal.

Abstract: A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.

Abstract: The disclosed embodiments relate to circuits that produce synchronized output signals. An input signal is received and used to produce a delayed input signal. The period of the input signal and the phase difference between the input signal and the delayed input signal are measured. The period of the input signal and the phase difference between the input signal and the delayed input signal are used to construct an output signal.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: A clock synchronization circuit (200, FIG. 2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an external clock signal (220) and a feedback signal (222) to evaluate the jitter present in the external clock signal. When the jitter falls within an acceptable range, the circuit operates in DLL mode. In DLL mode, the external clock signal is provided to the delay line, and the delayed external signal is output (224) from the circuit. If the jitter falls outside the acceptable range and the circuit is locked, the circuit is switched to PLL mode. In PLL mode, a clock signal based on the feedback signal is provided to the delay line, and the delayed feedback signal is output from the circuit. The PLL mode is only allowed to operate briefly before switching the circuit back into DLL mode.

Abstract: A clock signal generator providing an output clock signal synchronized with an input clock signal having an input clock frequency including a frequency dependent variable delay line to accommodate a wide range of operating frequencies. A clock signal synchronized with an input clock signal propagated through an input time delay and an output time delay is generated by delaying an input buffered clock signal by a first time delay based on the frequency of the input buffered clock signal, and further delaying the delayed input buffered clock signal by a second time delay to compensate for timing skew introduced by the input time delay, the output time delay and the process of delaying the input buffered clock signal.

Abstract: An electronic system includes a deskewing circuit configured to measure a delay and generate a synchronized signal according to the measured delay. The deskewing circuit may be configured to detect an overflow condition and respond accordingly, for example by asserting an overflow signal. Further, the deskewing circuit may be additionally or alternatively configured to detect successful measurement of the delay and respond, for example by executing a power saving and/or noise reducing procedure.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.