Patents by Inventor Tyler James

Tyler James has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080098301
    Abstract: A method for peer-to-portal broadcasting, including providing a web page for a portal, the web page including an inline frame (iFrame), receiving meta-data for media files selected by a user for broadcast to the portal, and dynamically generating source code for the iFrame upon request, the source code including instructions for a web browser (i) to request an XML document that includes meta-data for user-selected media files, (ii) to transform the XML document to an HTML document using an XSLT transformation, and (iii) to insert the resulting HTML document into the web page for the portal. A system and computer-readable storage media are also described and claimed.
    Type: Application
    Filed: February 28, 2007
    Publication date: April 24, 2008
    Inventors: Tyler James Black, Dylan John Hansen, Leonard Harley, Ronald Loren Kirkby, Kevin Justin Slagboom, Colby James Magee Smith, Ronald William Stevens, James Ormond Loucks, Seamus Gregory Davis O'Connor, Brian Charles Oraas, Bryn Adam Aspestrand
  • Publication number: 20080098101
    Abstract: A system for peer-to-web media broadcasting, including a plurality of publisher computers, for broadcasting media over the Internet, each publisher computer including a video transcoder, and an image processor, a plurality of HTTP web client computers for viewing broadcasted media, an application server for transmitting web page content to HTTP web client computers, including a database management system for storing and retrieving publisher authentication information, at least one switchboard server, for managing TCP/IP connections between online publisher computers and HTTP web client computers, a load balancer for distributing incoming client requests among the at least one switchboard server, and a storage volume that is mounted on each of the at least one switchboard servers, for caching portions of media received from publishing computers. A method and computer-readable storage media are also described and claimed.
    Type: Application
    Filed: October 20, 2006
    Publication date: April 24, 2008
    Inventors: Tyler James Black, Dylan John Hansen, Leonard Harley, Ronald Loren Kirkby, James Ormond Loucks, Seamus Gregory Davis O'Connor, Brian Charles Oraas, Kevin Justin Slagboom, Colby James Magee Smith, Ronald William Stevens, Bryn Adam Aspestrand
  • Patent number: 7225394
    Abstract: A circuit for correcting errors in an N times duplicated signal is described. The circuit comprises a plurality of AND gates, wherein each of the AND gates comprises a plurality of inputs for receiving a copy of the N times duplicated signal; and an OR gate having a plurality of inputs, wherein each input of the OR gate is connected to an output of one of the AND gates, wherein an output of the OR gate comprises the corrected signal.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: May 29, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Tyler James Johnson
  • Patent number: 7200778
    Abstract: In one embodiment, the invention is directed to a method of verifying conditions occurring during a simulation of a hardware design. The method comprises logging each occurrence of at least one specified condition in a first log; logging signals observed at an observability port in a second log; and comparing the first and second logs to determine whether for each occurrence of the at least one specified condition logged in the first log, a corresponding entry identifying a signal expected to be observed responsive to occurrence of the at least one specified condition is logged in the second log.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: April 3, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Tyler James Johnson
  • Patent number: 7188277
    Abstract: An integrated circuit (“IC”) comprising a plurality of logic modules. The IC further comprises a plurality of bus segments each associated with one of the logic modules; a debug bus interconnecting the bus segments in a ring; and a debug port connected to the debug bus for accessing debug data on the debug bus. Each bus segment takes in data from the logic module associated therewith and outputs the data to the debug bus to be forwarded to the next bus segment along the ring.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: March 6, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Tyler James Johnson
  • Patent number: 7146538
    Abstract: A bus interface module (“BIM”) connectable to a debug bus is described. In one embodiment, the BIM comprises a plurality of BIM segments connected in a ring such that an output of each BIM is connected to an input of a next BIM via the debug bus, the BIM comprising logic for receiving data from a previous BIM, logic for receiving data from local logic associated with the BIM, and logic for combining the previous BIM data with local logic data and transmitting the combined data to a next BIM.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: December 5, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Tyler James Johnson, Theodore Carter Briggs
  • Patent number: 7107394
    Abstract: In one embodiment, an apparatus is disclosed for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; and logic for comparing a value of the counter with a preselected register address on each count of the counter, wherein the logic for comparing comprises a comparator having an input connected to receive the preselected register address, an input connected to receive the value of the counter, and an output operable to drive a select signal of a multiplexer provided for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Tyler James Johnson
  • Patent number: 6949956
    Abstract: A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2N is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: September 27, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Tyler James Johnson
  • Patent number: 6928629
    Abstract: In one embodiment, the invention is directed to a method of processing a database comprising information regarding hardware design language (“HDL”) events occurring during a simulation of a hardware design. The method comprises identifying in the database all HDL events comprising observability events; obtaining from each of the identified observability HDL events information pertaining to a signal driving the identified observability HDL event observed on an observability bus; and creating a data structure comprising a plurality of entries, wherein each of the entries corresponds to one of the signals observed on the observability bus and contains signal information pertaining to the one of the observed signals.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: August 9, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Tyler James Johnson
  • Publication number: 20040222819
    Abstract: A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2N is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.
    Type: Application
    Filed: June 3, 2003
    Publication date: November 11, 2004
    Inventor: Tyler James Johnson
  • Publication number: 20040225974
    Abstract: In one embodiment, the invention is directed to a method of processing a database comprising information regarding hardware design language (“HDL”) events occurring during a simulation of a hardware design. The method comprises identifying in the database all HDL events comprising observability events; obtaining from each of the identified observability HDL events information pertaining to a signal driving the identified observability HDL event observed on an observability bus; and creating a data structure comprising a plurality of entries, wherein each of the entries corresponds to one of the signals observed on the observability bus and contains signal information pertaining to the one of the observed signals.
    Type: Application
    Filed: June 3, 2003
    Publication date: November 11, 2004
    Inventor: Tyler James Johnson
  • Publication number: 20040225973
    Abstract: In one embodiment, the invention is directed to a method of optimizing post-silicon test coverage for a system under test (“SUT”). The method comprises defining coverage data comprising Hardware Description Language (“HDL”) events; testing the SUT using a system exerciser connected to the SUT; comparing the results of the testing with the coverage data to identify underutilized areas of functionality of the SUT; and responsive to the comparing operation, performing additional tests.
    Type: Application
    Filed: June 3, 2003
    Publication date: November 11, 2004
    Inventor: Tyler James Johnson
  • Publication number: 20040225936
    Abstract: A circuit for correcting errors in an N times duplicated signal is described. The circuit comprises a plurality of AND gates, wherein each of the AND gates comprises a plurality of inputs for receiving a copy of the N times duplicated signal; and an OR gate having a plurality of inputs, wherein each input of the OR gate is connected to an output of one of the AND gates, wherein an output of the OR gate comprises the corrected signal.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 11, 2004
    Inventor: Tyler James Johnson
  • Publication number: 20040205404
    Abstract: An integrated circuit (“IC”) comprising a plurality of logic modules. The IC further comprises a plurality of bus segments each associated with one of the logic modules; a debug bus interconnecting the bus segments in a ring; and a debug port connected to the debug bus for accessing debug data on the debug bus. Each bus segment takes in data from the logic module associated therewith and outputs the data to the debug bus to be forwarded to the next bus segment along the ring.
    Type: Application
    Filed: March 28, 2003
    Publication date: October 14, 2004
    Inventor: Tyler James Johnson
  • Publication number: 20040194041
    Abstract: In one embodiment, the invention is directed to a method of verifying conditions occurring during a simulation of a hardware design. The method comprises logging each occurrence of at least one specified condition in a first log; logging signals observed at an observability port in a second log; and comparing the first and second logs to determine whether for each occurrence of the at least one specified condition logged in the first log, a corresponding entry identifying a signal expected to be observed responsive to occurrence of the at least one specified condition is logged in the second log.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Inventor: Tyler James Johnson
  • Publication number: 20040193962
    Abstract: A bus interface module (“BIM”) connectable to a debug bus is described. In one embodiment, the BIM comprises a plurality of BIM segments connected in a ring such that an output of each BIM is connected to an input of a next BIM via the debug bus, the BIM comprising logic for receiving data from a previous BIM, logic for receiving data from local logic associated with the BIM, and logic for combining the previous BIM data with local logic data and transmitting the combined data to a next BIM.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Inventors: Tyler James Johnson, Theodore Carter Briggs
  • Publication number: 20040193790
    Abstract: A method and apparatus for using a debug bus as a capture buffer are described. In one embodiment, the invention is directed to an apparatus for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; logic for comparing a value of the counter with a preselected register address on each count of the counter; and logic for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Inventor: Tyler James Johnson
  • Publication number: 20040111858
    Abstract: A method and apparatus for assembling a first thermoformed workpiece, such as a tab closure, to a second thermoformed workpiece, such as a lid.
    Type: Application
    Filed: September 18, 2003
    Publication date: June 17, 2004
    Applicant: DART CONTAINER CORPORATION
    Inventors: Ralph William MacKenzie, Tyler James DeLong, Ryan P. Gingras
  • Publication number: 20030219019
    Abstract: A method of inverse multiplexing and demultiplexing multiple ATM communication channels. This process is intended to maximize the use of bandwidth on all channels when the bandwidth conditions on each channel are fluctuating dynamically with time. In extreme cases, this method is intended to work even when one or more channels cease to operate. The multiplexing part of this method seeks to maximize the bandwidth along all communication links as well as maintaining a record of the bandwidth fluctuations along the channels. The demultiplexing part of this method seeks to accurately reconstruct the ATM cell stream that was inverse multiplexed across the multiple communication links by ordering the cells in the same order as they were sent. Two processes are presented by which this is done.
    Type: Application
    Filed: May 24, 2002
    Publication date: November 27, 2003
    Inventor: Tyler James Wilson