Patents by Inventor Tze-Chung Lin

Tze-Chung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250105019
    Abstract: A method is provided. The method includes: receiving a semiconductor structure having a first material and a second material; performing a first etch on the first material for a first duration under a first etching chemistry; and performing a second etch on the second material for a second duration under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry. The first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry.
    Type: Application
    Filed: December 10, 2024
    Publication date: March 27, 2025
    Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
  • Publication number: 20250089331
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a stack structure over a substrate, and the stack structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked. The method includes forming a dummy gate electrode over the first semiconductor layers and the second semiconductor layers, and forming a gate spacer layer adjacent to the dummy gate electrode. The method includes removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers, and forming a dummy dielectric layer in the recess after the dummy gate electrode is formed. The dummy dielectric layer is between two adjacent first semiconductor layers. The method includes replacing the dummy gate electrode and the dummy dielectric layer with a gate structure.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Chung LIN, Han-Yu LIN, Li-Te LIN, Pinyen LIN
  • Patent number: 12224210
    Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
  • Patent number: 12217961
    Abstract: A method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process. The lateral etching process includes a radical etching process and a chemical etching process. Alternatively, the lateral etching process includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chien Kuang, Tze-Chung Lin, Li-Te Lin
  • Publication number: 20250040238
    Abstract: In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Inventors: Yu-Wei Lu, Kenichi Sano, Tze-Chung Lin, Fang-Wei Lee, Chia-Chien Kuang, Yi-Chen Lo, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 12198939
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Han-Yu Lin, Li-Te Lin, Tze-Chung Lin, Fang-Wei Lee, Yi-Lun Chen, Jung-Hao Chang, Yi-Chen Lo, Fo-Ju Lin, Kenichi Sano, Pinyen Lin
  • Patent number: 12154970
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first semiconductor layers and second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layers and second semiconductor layers to form a S/D trench. The method also includes removing the second semiconductor layers to form a recess connected to the S/D trench. The method includes forming a dummy dielectric layer in the recess after the dummy gate structure is formed, and the dummy dielectric layer is exposed by the S/D trench. The method includes removing a portion of the dummy dielectric layer to form a cavity and forming an inner spacer layer in the cavity.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Chung Lin, Han-Yu Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20240347345
    Abstract: A semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. The processing chamber includes a sidewall and a top surface. The semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. The gas distribution plate defines a portion of the top surface of the processing chamber. From a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin
  • Publication number: 20240321642
    Abstract: A method of fabricating a semiconductor device includes forming, over a substrate, alternating layers of a first semiconductor layer formed of a first semiconductor material and a second semiconductor layer formed of a second semiconductor material, the first semiconductor layers including a first, a second, and a third sub-layers; patterning the alternating layers of the first and the second semiconductor layers to form stacks of the alternating layers; and exposing, under etch conditions, lateral edges of the alternating layers to an etchant to selectively etch recesses in the lateral edges of the first, the second, and the third sub-layers, such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer.
    Type: Application
    Filed: June 4, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chung-Shu Wu, Tze-Chung Lin, Shih-Chiang Chen, Hsiu-Hao Tsao, Chun-Hung Lee
  • Publication number: 20240290854
    Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company. Ltd.
    Inventors: Tze-Chung LIN, Han-Yu LIN, Pinyen LIN, Fang-Wei LEE, Li-Te LIN
  • Publication number: 20240234549
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Yu LIN, Chansyun David YANG, Fang-Wei LEE, Tze-Chung LIN, Li-Te LIN, Pinyen LIN
  • Patent number: 12033895
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a semiconductor substrate. Alternating layers of a first semiconductor layer and a second semiconductor layer are formed. The first semiconductor layer is formed of a first semiconductor material, the second semiconductor layer formed of a second semiconductor material different from the first semiconductor material. The alternating layers of the first semiconductor layer and the second semiconductor layer are patterned to form stacks of the alternating layers and to expose lateral edges of the alternating layers in the stacks. Under etch conditions, the lateral edges of the alternating layers in the stacks are exposed to etchant to selectively etch recesses in the lateral edges of the first semiconductor layer such that a size of the recesses is substantially uniform.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Shu Wu, Tze-Chung Lin, Shih-Chiang Chen, Hsiu-Hao Tsao, Chun-Hung Lee
  • Patent number: 12033863
    Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin
  • Patent number: 12021125
    Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: June 25, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tze-Chung Lin, Pinyen Lin, Fang-Wei Lee, Li-Te Lin, Han-Yu Lin
  • Patent number: 11973129
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Yu Lin, Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20240097011
    Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
  • Publication number: 20240006177
    Abstract: A method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process. The lateral etching process includes a radical etching process and a chemical etching process. Alternatively, the lateral etching process includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chien KUANG, Tze-Chung LIN, Li-Te LIN
  • Patent number: 11855192
    Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: December 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu Lin, Fang-Wei Lee, Kai-Tak Lam, Raghunath Putikam, Tzer-Min Shen, Li-Te Lin, Pinyen Lin, Cheng-Tzu Yang, Tzu-Li Lee, Tze-Chung Lin
  • Patent number: 11830928
    Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20230282520
    Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.
    Type: Application
    Filed: May 8, 2023
    Publication date: September 7, 2023
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji