Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.

Abstract: A semiconductor device structure is provided. The semiconductor device includes a first nanowire structure over a second nanowire structure, a gate stack wrapping around the first nanowire structure and the second nanowire structure, a source/drain feature adjoining the first nanowire structure and the second nanowire structure, a gate spacer layer over the first nanowire structure and between the gate stack and the source/drain feature, and an inner spacer layer between the first nanowire structure and the second nanowire structure and between the gate stack and the source/drain feature. The gate spacer layer has a first carbon concentration, the inner spacer has a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.

Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.

Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method also includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers. The method further includes removing a portion of the first semiconductor layers and second semiconductor layers to form a trench, and removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers. The method includes forming a dummy dielectric layer in the recess, and removing a portion of the dummy dielectric layer to form a cavity. The method also includes forming an inner spacer layer in the cavity.

Abstract: A method of fabricating a semiconductor device includes forming a structure including multiple nanowires vertically stacked above a substrate; depositing a dielectric material layer wrapping around the nanowires; performing a treatment process to a surface portion of the dielectric material layer; selectively etching the surface portion of the dielectric material layer; repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed; and forming a gate structure engaging the nanowires.

Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.

Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.

Abstract: A method of fabricating a semiconductor device includes forming a structure including multiple nanowires vertically stacked above a substrate; depositing a dielectric material layer wrapping around the nanowires; performing a treatment process to a surface portion of the dielectric material layer; selectively etching the surface portion of the dielectric material layer; repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed; and forming a gate structure engaging the nanowires.

Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.