Abstract: A level shift circuit includes: a first transistor coupled to a first reference voltage for receiving a first voltage input signal; a second transistor coupled to a second reference voltage; a first diode-connected transistor coupled between the second transistor and the first diode-connected transistor; a third transistor coupled to the first reference voltage and the second transistor, for receiving a second voltage input signal, wherein the first voltage input signal is an inverse version of the second voltage input signal; a fourth transistor coupled to the second reference voltage and the first transistor; a second diode-connected transistor coupled between the fourth transistor and the third transistor; and a fifth transistor coupled to the second voltage input signal, the first reference voltage, and the fourth transistor, wherein a level-shifted output signal corresponding to the first voltage input signal is generated at an output node of the fourth transistor.

Abstract: A level shift circuit includes: a first transistor coupled to a first reference voltage for receiving a first voltage input signal; a second transistor coupled to a second reference voltage; a first diode-connected transistor coupled between the second transistor and the first diode-connected transistor; a third transistor coupled to the first reference voltage and the second transistor, for receiving a second voltage input signal, wherein the first voltage input signal is an inverse version of the second voltage input signal; a fourth transistor coupled to the second reference voltage and the first transistor; a second diode-connected transistor coupled between the fourth transistor and the third transistor; and a fifth transistor coupled to the second voltage input signal, the first reference voltage, and the fourth transistor, wherein a level-shifted output signal corresponding to the first voltage input signal is generated at an output node of the fourth transistor.

Abstract: A delay cell for delaying an input data signal to generate an output data signal includes a logic circuit and a bias current generator. The logic circuit is used for processing the input data signal to generate the output data signal. The bias current generator is coupled to the logic circuit for providing a first bias current to the logic circuit to control a delay time of the delay cell based on a process corner at which the delay cell is manufactured in a wafer. The bias current generator includes a first transistor coupled between a first power supply and the logic circuit for steering the first bias current of the logic circuit, wherein the first transistor is biased by a first bias voltage.

Abstract: A display device includes a display panel, a timing controller generating a timing controlling signal having a plurality of states, each state representing both data information and clock information, and a source driver receiving and decoding the timing controlling signal to recover the data information and the clock information for generating a clock signal and a data signal for driving the display panel.

Abstract: A chip-on-glass panel device includes a glass substrate having a pixel area, an integrated circuit area, and a fan out area, the fan out area located between the pixel area and the IC area, a plurality of integrated circuit devices arranged within the integrated area of the glass substrate, each of the plurality of integrated circuit devices have an active surface, a plurality of output pads, each arranged on the active surface, and a plurality of signal pads/gamma pads, each arranged on the active surface, and a plurality of signal wires/gamma wires, each having a curved shape geometry and disposed within the fan out area, for connecting the plurality of signal pads/gamma pads of adjacent ones of the plurality of integrated circuit devices through the fan out area.

Abstract: A display includes an array of pixel circuits and data drivers to drive the pixel circuits. The data drivers include a first data driver to receive pixel data according to a first clock frequency and to forward some of the pixel data to a second data driver according to a second clock frequency, the second clock frequency being different from the first clock frequency.

Abstract: A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A display includes an array of pixel circuits and data drivers to drive the pixel circuits. The data drivers include a first data driver to receive pixel data according to a first clock frequency and to forward some of the pixel data to a second data driver according to a second clock frequency, the second clock frequency being different from the first clock frequency.

Abstract: The invention relates to a signal driving system for a display. The signal driving system comprises: a signal controller, a flexible connector and a plurality of driving devices. The signal controller is used to produce a first control signal. The flexible connector is connected to the signal controller, and used to receive the first control signal. One of the driving devices is connected to the flexible connector. The driving devices connect in cascade. Each driving device comprises a data input port, a data output port and a driving signal output port. The data input port receives the first control signal or a second control signal. The data output port outputs the second control signal. According to the first control signal or the second control signal, the driving signal output port transmits a driving signal. The signal driving system of the invention can make the data output port of the driving device transmit the second control signal to the next driving device.

Abstract: One embodiment of the invention includes an liquid crystal display (LCD) with multiple polarity signal lines that control output buffer blocks so that at least one voltage polarity of a signal transmitted via a data line controlled by a first output buffer block inverts non-simultaneously with at least one voltage polarity of a signal transmitted via a data line controlled by a second output buffer block.

Abstract: A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: An LCD monitor including M scan sections is provided for displaying one frame in one frame time. Each of the M scan section includes several scan lines. Each scan line corresponds to one pixel. A frame time includes M scan-section times corresponding to one of the M scan sections respectively. Each scan-section time includes one black-frame-inserting time and several scan-line times. All pixels corresponding to the (S+N)th scan section is turned black during the black-frame-inserting time of the Sth scan section time. The scan lines in the Sth scan section are enabled during the scan-line times of the Sth scan-section time. S is an integer which is smaller or equal to M.

Abstract: A display includes an array of pixel circuits and data drivers to drive the pixel circuits. The data drivers include a first data driver to receive pixel data according to a first clock frequency and to forward some of the pixel data to a second data driver according to a second clock frequency, the second clock frequency being different from the first clock frequency.

Abstract: A driving circuit of a flat panel display device includes a horizontal bus, a plurality of horizontal driver ICs, a vertical bus, and a plurality of vertical driver ICs. The horizontal driver IC is operative to decode N-types of vertical driving signals output from the horizontal bus, so as to transmit the N-type vertical driving signals to the corresponding vertical driver IC via a vertical signal line of the vertical bus.