Abstract: Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Abstract: One or more computing devices, systems, and/or methods for cross-domain action prediction are provided. Action sequence embeddings are generated based upon a textual embedding and a graph embedding utilizing past user action sequences corresponding to sequences of past actions performed by users across a plurality of domains. An autoencoder is trained to utilize the action sequence embeddings to project the action sequence embeddings to obtain intent space vectors. A service switch classifier is trained using the intent space vectors. In response to the service switch classifier predicting that a current user will switch from a current domain to a next domain, the current user is provided with a recommendation of an action corresponding to the next domain.

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Abstract: A flyback power converter includes: a power transformer, a primary side control circuit, a secondary side control circuit, and an active clamp snubber including a snubber switch and a control signal generation circuit. The control signal generation circuit controls the snubber switch to be conductive during a soft switching period in an OFF period of a primary side switch within a switching period of the switching signal, whereby the primary side switch achieves soft switching. A starting time point of the soft switching period is determined by a current threshold, so that a secondary side current is not lower than the current threshold at the starting time point, whereby the secondary side control circuit keeps the SR switch conductive at the starting time point. The secondary side control circuit turns OFF the SR switch when the secondary side current is lower than the current threshold.

Abstract: A method for optimizing a data model is used in a device. The device acquires data information and selecting at least two data models according to the data information, and utilizes the data information to train the at least two data models. The device acquires each accuracy of the at least two data models, determines a target data model which has greatest accuracy between the at least two data models, and optimizes the target data model.

Abstract: A flyback power converter circuit includes a transformer, a blocking switch, a primary side switch, a primary side controller circuit and a secondary side controller circuit. The transformer is coupled between an input voltage and an internal output voltage in an isolated manner. The blocking switch controls the electric connection between the internal output voltage and an external output voltage. In a standby mode, the internal output voltage is regulated to a standby voltage, and the blocking switch is controlled to be OFF; in an operation mode, the internal output voltage is regulated to an operating voltage, and the blocking switch is controlled to be ON, such that the external output voltage has the operating voltage. The standby voltage is smaller than the operating voltage, so that the power consumption of the flyback power converter circuit is reduced in the standby mode.

Abstract: A method of detecting product defects obtains an image of a product and sets a region of interest (ROI) of the image. A first contour of a first target object is detected in the region of interest. The image is detected according to the first contour to obtain a corrected image. A position difference between the first contour and a second target object in the region of interest is obtained. A second contour of the second target object is detected in the corrected image according to the position difference. A first image area corresponding to the first contour and a second image area corresponding to the second contour are segmented and input into an autoencoder. According to outputs of the autoencoder, whether the product is defective is determined. A detection result of the product is output. The method can detect defects on products quickly and accurately.

Abstract: An optical photographing lens assembly includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements of the optical photographing lens assembly has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the first lens element is concave in a paraxial region thereof. The object-side surface of the first lens element is aspheric and has at least one critical point in an off-axis region thereof.

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

Abstract: A liquid-cooled heat dissipation device is disclosed, comprising a main body, a centrifugal pump, an inlet pipe, an outlet pipe, a centrifugal fan and a motor. The main body comprises a shaft hole, liquid flow channels and airflow channels. The centrifugal pump guides a cooling liquid through the inlet pipe, main body and outlet pipe. The centrifugal fan guides air into the main body axially from the shaft hole. After passing through the centrifugal fan, the air forms centrifugal airflows and leaves the body radially through the airflow channels. With an extended flow path of the cooling liquid and the radial flow of the centrifugal airflow provided by the present invention, the temperature of the cooling liquid may be quickly reduced and the cooling effect may be improved. Thus, the structure is compact, small, light-weight, easy-to-assemble.

Abstract: A method for detecting defects in images, is employed in a computer device, and stored in a storage medium. The method trains an autoencoder model using unblemished images, inputting an image to be detected into the autoencoder model, and obtaining a reconstructed image. An image error is calculated between the image to be detected and the reconstructed image, and the image error is inputted into a student's t-distribution and a calculation result is obtained. In response that the calculation result falls within a preset defect determination criterion range, the image to be detected is determined to be an unblemished image. In response that the calculation result does not fall within the preset defect determination criterion range, the image to be detected is determined to be a defective image. The method improves the efficiency and accuracy of defect detection.

Abstract: A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit, each of the plurality of power-amplifier chips being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

Abstract: A method for detecting cells in images using an autoencoder, a computer device, and a storage medium extracts a first feature vector from each of a plurality of sample medical images. The first feature vector is inputted into an autoencoder, and a first latent feature of each of the plurality of sample medical images is extracted. A first predicted value of a number of cells in each of the plurality of sample medical images is generated based on the first latent feature. The first latent feature is inputted into the autoencoder, and a plurality of reconstructed images are obtained. The autoencoder is optimized based on the plurality of reconstructed images and the first predicted value. This method can be run in the computer device to improve efficiency of detection from images.

Abstract: A method for selecting a deep learning network which is optimal for solving an image processing task obtaining a type of the image processing task, selecting a data set according to the type of problem, and dividing selected data set into training data and test data. Similarities between different training data are calculated, and a batch size of the training data is adjusted according to the similarities of the training data. A plurality of deep learning networks is selected according to the type of problem, and the plurality of deep learning networks is trained through the training data to obtain network models. Each of the network models is tested through the test data, and the optimal deep learning network with the best test result is selected from the plurality of deep learning networks appropriate for image processing.

Abstract: The present invention discloses a power converter, a switch control circuit, and a short circuit detection method for current sensing resistor of the power converter. The power converter includes: a transformer, a power switch, a current sensing resistor and a switch control unit. The current sensing resistor has one end coupled to the power switch and another end coupled to ground. The switch control unit generates the operation signal to control the power switch. The switch control unit generates a first sample-and-hold voltage at a first time point and a second sample-and-hold voltage at a second time point according to a voltage across the current sensing resistor. When a voltage difference between the first sample-and-hold voltage and the second sample-and-hold voltage is smaller than a reference voltage, it is determined that a short circuit occurs in the current sensing resistor.

Abstract: A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.

Abstract: An image capturing optical lens assembly includes five lens elements, in order from an object side to an image side along an optical path, being a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The fourth lens element with positive refractive power has an image-side surface being convex in a paraxial region thereof. The fifth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. At least one of surfaces of the fifth lens element includes at least one critical point in an off-axis region thereof.

Abstract: A spike suppression circuit includes a wide bandgap transistor, a first transistor, a clamping circuit, and a capacitor. The wide bandgap transistor is depletion-type. The first transistor is coupled in series with the wide bandgap transistor. The clamping circuit provides a voltage difference, and is coupled to a common node between the wide bandgap transistor and the first transistor. The capacitor provides a supply voltage for the clamping circuit. When the first transistor is turned off, the capacitor can recycle spike energy at the common node.