Abstract: The present invention provides a substrate structure and a method of fabricating the substrate structure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulating protection layer, and removing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.

Abstract: A method for initializing a peripheral device and an electronic device using the method. The electronic device includes one or more peripheral devices having registers, a memory having a data storing module, and an instruction capturing module. The instruction capturing module captures a plurality of hardware register settings from a driver execution process of the one or more peripheral devices, stores the plurality of hardware register settings in the data storing module, and serializes or concatenates the plurality of hardware register settings to form serialized hardware register settings, when the electronic device is performing a non-hibernation resume or non-wakeup cold boot to execute an initialization process of the one or more peripheral devices. The one or more peripheral devices are initialized by the serialized hardware register settings, when the electronic device is performing cold boot again due to a hibernation resume or wakeup to execute the initialization process.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

Abstract: A system suspending method, a system resuming method and a computer system using the same are provided. The system resuming method of the computer system is applied for resuming the computer system to be a normal status (S0 status) from a suspend-to-ram status (S3 status) or a suspend-to-disk status (S4 status). The computer system includes a plurality of peripheral devices and a central processing unit. The peripheral devices are classified into a first group and a second group. The system resuming method includes the following steps. The central processing unit is powered on. Then, the peripheral devices belonging in the first group are resumed. Next, the computer system is thawed.

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

Abstract: An electronic apparatus and a method for resuming from hibernation are disclosed. The electronic apparatus comprises an external storage, a main memory, an image generating circuit and a page moving circuit. The image generating circuit writes pages from the main memory into the external storage to generate a hibernation image file during a hibernation process. The page moving circuit according to the hibernation image file sequentially writes the pages from the external storage back to a continuous page range of the main memory during a resume process. The resume process is later than the hibernation process.

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

Abstract: A package substrate includes a substrate body having a first surface and a second surface opposite to the first surface; a first circuit layer formed on the first surface and having first conductive pads; a first dielectric layer formed on the first surface and the first circuit; a second circuit layer formed on the first dielectric layer and having second conductive pads; a third circuit layer formed on the second surface and having third conductive pads; a second dielectric layer formed on the second surface and the third circuit layer; a fourth circuit layer formed on the second dielectric layer and having fourth conductive pads; through holes penetrating through the first and second surfaces, and the first and second dielectric layers; and conductive vias penetrating through the through holes and electrically connected to the first, second, third and fourth conductive pads.

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

Abstract: The present invention provides a substrate structure and a method of fabricating the substrate substrure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulative protection layer, and remvoing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.

Abstract: A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated.

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

Abstract: A package substrate and a method of fabricating the same are provided. The method includes providing a substrate body having a first surface, a second surface opposing the first surface, a plurality of first electrical connecting pads disposed on the first surface; mounting a metal board on the first electrical connecting pads; and patterning the metal board so as to define a plurality of metal pillars corresponding to the first electrical connecting pads. Therefore, drawbacks of raw edges and unequal heights of the metal pillars can be obviated.

Abstract: A method for fabricating a coreless packaging substrate is provided, which includes: forming a dielectric layer on a conductive plate having a plurality of conductive pads; forming a circuit layer on the dielectric layer and forming in the dielectric layer a plurality of conductive vias that electrically connect the circuit layer and the conductive pads; and removing a portion of the conductive plate so as to cause the remaining portion of the conductive plate to form a plurality of conductive elements, thereby dispensing with a core layer and reducing the material and fabrication cost.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.