Patents by Inventor Tzu Chung TSAI

Tzu Chung TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210005487
    Abstract: In some embodiments, the present disclosure relates to a process tool which includes a housing that defines a vacuum chamber. A wafer chuck is in the housing, and a carrier wafer is on the wafer chuck. A structure that is used for deposition processes is arranged at a top of the housing. A camera is integrated on the wafer chuck such that the camera faces a top of the housing. The camera is configured to wirelessly capture images of the structure used for deposition processes within the housing. Outside of the housing is a wireless receiver. The wireless receiver is configured to receive the images from the camera while the vacuum chamber is sealed.
    Type: Application
    Filed: June 22, 2020
    Publication date: January 7, 2021
    Inventors: Tzu-Chung Tsai, Chii-Ming Wu, Hai-Dang Trinh
  • Patent number: 10748798
    Abstract: In some embodiments, the present disclosure relates to a process tool which includes a housing that defines a vacuum chamber. A wafer chuck is in the housing and a carrier wafer is on the wafer chuck. A camera is integrated on the wafer chuck such that the camera faces a top of the housing. The camera is configured to wirelessly capture images of an object of interest within the housing. Outside of the housing is a wireless receiver. The wireless receiver is configured to receive the images from the camera while the vacuum chamber is sealed.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung Tsai, Chii-Ming Wu, Hai-Dang Trinh
  • Patent number: 10720581
    Abstract: The present disclosure is directed to resistive random access memory (RRAM) structures with a bottom electrode barrier stack. For example, the RRAM structure includes: (i) a bottom electrode having a conductive material and a layer stack, where the layer stack covers a bottom surface and a side surface of the conductive material and is interposed between the conductive material and an underlying conductive structure; (ii) a resistance-switching layer that is disposed on the bottom electrode and opposite to the conductive structure; and (iii) a top electrode that is disposed on the resistance-switching layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu Chung Tsai, Yan-Chi Chen, Hsia-Wei Chen
  • Publication number: 20200136039
    Abstract: The present disclosure is directed to resistive random access memory (RRAM) structures with a bottom electrode barrier stack. For example, the RRAM structure includes: (i) a bottom electrode having a conductive material and a layer stack, where the layer stack covers a bottom surface and a side surface of the conductive material and is interposed between the conductive material and an underlying conductive structure; (ii) a resistance-switching layer that is disposed on the bottom electrode and opposite to the conductive structure; and (iii) a top electrode that is disposed on the resistance-switching layer.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu Chung TSAI, Yan-Chi CHEN, Hsia-Wei CHEN