Patents by Inventor Tzu-Chung Wang

Tzu-Chung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930498
    Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
  • Patent number: 10886180
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Tzu-Chung Wang, Kai-Tai Chang, Wei-Sheng Yun
  • Publication number: 20200343302
    Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
  • Patent number: 10797174
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Publication number: 20200273996
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
  • Publication number: 20200273997
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
  • Patent number: 10707347
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
  • Patent number: 10685474
    Abstract: The present invention provides a method for repairing incomplete 3D depth image using 2D image information. The method includes the following steps: obtaining 2D image information and 3D depth image information; dividing 2D image information into 2D reconstruction blocks and 2D reconstruction boundaries, and corresponding to 3D reconstruction of blocks and 3D reconstruction boundaries; analyzing each 3D reconstruction block, partitioning into residual-surface blocks and repaired blocks; and proceeding at least one 3D image reconstruction, which extends with the initial depth value of the 3D depth image of each of the residual-surface block and covers all the corresponding repaired block to form a repair block and to achieve the purpose of repairing incomplete 3D depth images using 2D image information.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: June 16, 2020
    Assignee: NATIONAL CENTRAL UNIVERSITY
    Inventors: Yeh-Wei Yu, Chi-Chung Lau, Ching-Cherng Sun, Tsung-Hsun Yang, Tzu-Kai Wang, Jia-Ching Wang, Chien-Yao Wang, Kuan-Chung Wang
  • Publication number: 20200185597
    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Kun-Ju Li, Hsin-Jung Liu, I-Ming Tseng, Chau-Chung Hou, Yu-Lung Shih, Fu-Chun Hsiao, Hui-Lin Wang, Tzu-Hsiang Hung, Chih-Yueh Li, Ang Chan, Jing-Yin Jhang
  • Publication number: 20200158646
    Abstract: A surface-enhanced Raman scattering (SERS) detection method is provided for detecting a target analyte in a sample. The SERS detection method generally includes the steps of: (a). preparing an extract of the sample; (b). introducing the sample extract onto a SERS substrate, causing the target analyte to be absorbed in the SERS substrate; (c). introducing a volatile organic solvent onto the SERS substrate to have the target analyte of the sample extract dissolved and comes out of the SERS substrate; (d). irradiating the SERS substrate with light to evaporate the volatile organic solvent, leaving a more condensed target analyte on the SERS substrate; (e). irradiating the condensed target analyte with laser light to have the target analyte penetrate deeply into the SERS substrate; and (f). performing Raman measurement with a laser beam focusing on the SERS substrate to analyze the target analyte.
    Type: Application
    Filed: July 20, 2017
    Publication date: May 21, 2020
    Inventors: CHAO-MING TSEN, CHING-WEI YU, WEI-CHUNG CHAO, YUNG-HSIANG WANG, CHENG-CHIEN LI, SHAO-KAI LIN, TZU-HUNG HSU, CHANG-JUNG WEN
  • Publication number: 20200127138
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: January 23, 2019
    Publication date: April 23, 2020
    Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
  • Publication number: 20200105609
    Abstract: A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.
    Type: Application
    Filed: August 8, 2019
    Publication date: April 2, 2020
    Inventors: Tzu-Chung WANG, Tung Ying LEE
  • Publication number: 20200098876
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.
    Type: Application
    Filed: May 30, 2019
    Publication date: March 26, 2020
    Inventors: Tung Ying LEE, Tzu-Chung WANG, Kai-Tai CHANG, Wei-Sheng YUN
  • Publication number: 20200075716
    Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
  • Publication number: 20200075718
    Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
    Type: Application
    Filed: October 10, 2019
    Publication date: March 5, 2020
    Inventors: Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
  • Publication number: 20200058784
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Publication number: 20200058763
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Application
    Filed: September 5, 2019
    Publication date: February 20, 2020
    Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Publication number: 20200035013
    Abstract: The present invention provides a method for repairing incomplete 3D depth image using 2D image information. The method includes the following steps: obtaining 2D image information and 3D depth image information; dividing 2D image information into 2D reconstruction blocks and 2D reconstruction boundaries, and corresponding to 3D reconstruction of blocks and 3D reconstruction boundaries; analyzing each 3D reconstruction block, partitioning into residual-surface blocks and repaired blocks; and proceeding at least one 3D image reconstruction, which extends with the initial depth value of the 3D depth image of each of the residual-surface block and covers all the corresponding repaired block to form a repair block and to achieve the purpose of repairing incomplete 3D depth images using 2D image information.
    Type: Application
    Filed: November 19, 2018
    Publication date: January 30, 2020
    Inventors: Yeh-Wei YU, Chi-Chung LAU, Ching-Cherng SUN, Tsung-Hsun YANG, Tzu-Kai WANG, Jia-Ching WANG, Chien-Yao WANG, Kuan-Chung WANG
  • Patent number: D860308
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 17, 2019
    Assignee: Taiwan Hopax Chemicals Mfg. Co., Ltd.
    Inventors: Chin-Chung Tsai, Tzu-Jung Wang, Tsung-Tien Kuo
  • Patent number: D860309
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 17, 2019
    Assignee: Taiwan Hopax Chemicals Mfg. Co., Ltd.
    Inventors: Chin-Chung Tsai, Tzu-Jung Wang, Tsung-Tien Kuo