Patents by Inventor Tzu-Han Lin

Tzu-Han Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Publication number: 20240097661
    Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Huaixin XIAN, Tzu-Ying LIN, Liu HAN, Jerry Chang Jui KAO, Qingchao MENG, Xiangdong CHEN
  • Publication number: 20240088027
    Abstract: An integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. The guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. The first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. The third metal layer is above the second metal layer. All metal lines in the second metal layer that are part of the guard ring extend in the first direction.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Chiao-Han LEE, Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20240087945
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Tsai-Hao HUNG, Ping-Cheng KO, Tzu-Yang LIN, Fang-Yu LIU, Cheng-Han WU
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20220131056
    Abstract: A UV LED package includes a substrate having a dam, a LED die on the substrate, a lens bonded to the substrate, an extraction layer covering a light emitting surface of the LED die, and a lens sealing layer between the lens and the dam. The extraction layer can be formed to provide a precise gap G between the lens and the light emitting diode (LED). In addition, the materials for the lens and the extraction layer can be selected, and the gap G can be precisely dimensioned, to reduce refraction and reflection, to improve radiation extraction, to reduce power radiance, and to improve the efficiency of the UV LED package.
    Type: Application
    Filed: November 16, 2021
    Publication date: April 28, 2022
    Applicant: TSLC CORPORATION
    Inventors: TZU-YING LIN, PO-WEI LEE, SHENG-LUNG CHANG, TZU-HAN LIN
  • Publication number: 20210111318
    Abstract: A UV LED package includes a substrate having a dam, a LED die on the substrate, a lens bonded to the substrate, an extraction layer covering a light emitting surface of the LED die, and a lens sealing layer between the lens and the dam. The extraction layer can be formed to provide a precise gap G between the lens and the light emitting diode (LED). In addition, the materials for the lens and the extraction layer can be selected, and the gap G can be precisely dimensioned, to reduce refraction and reflection, to improve radiation extraction, to reduce power radiance, and to improve the efficiency of the UV LED package.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 15, 2021
    Applicant: TSLC CORPORATION
    Inventors: TZU-YING LIN, PO-WEI LEE, SHENG-LUNG CHANG, TZU-HAN LIN
  • Patent number: 10256217
    Abstract: A light emitting device includes a circuitry substrate and multiple light emitting diodes (LEDs) bonded to the circuitry substrate in a spaced array. The light emitting device also includes a continuous and substantially flat wavelength conversion member covering the light emitting diodes (LEDs) configured to convert the electromagnetic radiation emitted by the light emitting diodes (LEDs) into another wavelength range. The light emitting device also includes a planarized layer configured to support the wavelength conversion member on the circuitry substrate. The light emitting device can also include a light shaper on the wavelength conversion member configured to form emitting windows for the electromagnetic radiation transmitted through the wavelength conversion member forming an output light beam having a desired emitting window size, shape, and edge and to block and minimize scattered electromagnetic radiation from the wavelength conversion layer.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: April 9, 2019
    Assignee: TSLC CORP.
    Inventors: Po-Wei Lee, C. Chu, Tzu-Han Lin
  • Publication number: 20180342486
    Abstract: A light emitting device includes a circuitry substrate and multiple light emitting diodes (LEDs) bonded to the circuitry substrate in a spaced array. The light emitting device also includes a continuous and substantially flat wavelength conversion member covering the light emitting diodes (LEDs) configured to convert the electromagnetic radiation emitted by the light emitting diodes (LEDs) into another wavelength range. The light emitting device also includes a planarized layer configured to support the wavelength conversion member on the circuitry substrate. The light emitting device can also include a light shaper on the wavelength conversion member configured to form emitting windows for the electromagnetic radiation transmitted through the wavelength conversion member forming an output light beam having a desired emitting window size, shape, and edge and to block and minimize scattered electromagnetic radiation from the wavelength conversion layer.
    Type: Application
    Filed: May 29, 2017
    Publication date: November 29, 2018
    Applicant: TSLC CORPORATION
    Inventors: Po-Wei Lee, C. Chu, Tzu-Han Lin
  • Patent number: 9484385
    Abstract: An image sensor package and method for fabricating the same is provided. The image sensor package includes a first substrate comprising a via hole therein, a driving circuit and a first conductive pad thereon. A second substrate comprising a photosensitive device and a second conductive pad thereon is bonded to the first substrate, so that the driving circuit, formed on the first substrate, can electrically connect to and further control the photosensitive device, formed on the second substrate. A solder ball is formed on a backside of the first substrate and electrically connects to the via hole for transmitting a signal from the driving circuit. Because the photosensitive device and the driving circuit are fabricated individually on the different substrates, fabrication and design thereof is more flexible. Moreover, the image sensor package is relatively less thick, thus, the dimensions thereof are reduced.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: November 1, 2016
    Assignee: VisEra Technologies Company Limited
    Inventors: Jui-Ping Weng, Jang-Cheng Hsieh, Tzu-Han Lin, Pai-Chun Peter Zung
  • Publication number: 20160079304
    Abstract: An image sensor package and method for fabricating the same is provided. The image sensor package includes a first substrate comprising a via hole therein, a driving circuit and a first conductive pad thereon. A second substrate comprising a photosensitive device and a second conductive pad thereon is bonded to the first substrate, so that the driving circuit, formed on the first substrate, can electrically connect to and further control the photosensitive device, formed on the second substrate. A solder ball is formed on a backside of the first substrate and electrically connects to the via hole for transmitting a signal from the driving circuit. Because the photosensitive device and the driving circuit are fabricated individually on the different substrates, fabrication and design thereof is more flexible. Moreover, the image sensor package is relatively less thick, thus, the dimensions thereof are reduced.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Inventors: Jui-Ping WENG, Jang-Cheng HSIEH, Tzu-Han LIN, Pai-Chun Peter ZUNG
  • Patent number: 9231012
    Abstract: An image sensor package and method for fabricating the same is provided. The image sensor package includes a first substrate comprising a via therein, a driving circuit and a first conductive pad thereon. A second substrate comprising a photosensitive device and a second conductive pad thereon is bonded to the first substrate, so that the driving circuit, formed on the first substrate, can electrically connect to and further control the photosensitive device, formed on the second substrate. A solder ball is formed on a backside of the first substrate and electrically connects to the via for transmitting a signal from the driving circuit. Because the photosensitive device and the driving circuit are fabricated individually on the different substrates, fabrication and design thereof is more flexible. Moreover, the image sensor package is relatively less thick, thus, the dimensions thereof are reduced.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: January 5, 2016
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Jui-Ping Weng, Jang-Cheng Hsieh, Tzu-Han Lin, Pai-Chun Peter Zung
  • Patent number: 8524521
    Abstract: A wafer level image module includes a photo sensor for outputting an electrical signal upon receiving light, a lens set for focusing incident light onto the photo sensor, and an adjustment member disposed between the photo sensor and the lens set for controlling the distance between the photo sensor and the lens set to compensate the focus offset of the photo sensor for enabling the lens set to accurately focus the incident light onto the photo sensor in an in-focus manner so as to provide a high image quality.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: September 3, 2013
    Assignees: VisEra Technologies Company Limited, OmniVision Technologies, Inc.
    Inventors: Hsiao-Wen Lee, Pai-Chun Peter Zung, Tzu-Han Lin
  • Patent number: 8502257
    Abstract: A light-emitting diode package is provided. The light-emitting diode package comprises a substrate and a first metal layer disposed over the substrate. A solder layer is disposed on the first metal layer and a light-emitting diode chip is disposed on the solder layer, wherein the light-emitting diode chip comprises a conductive substrate and a multilayered epitaxial structure formed on the conductive substrate, and wherein the conductive substrate is adjacent to the solder layer.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: August 6, 2013
    Assignee: VisEra Technologies Company Limited
    Inventors: Kuo-Ching Chang, Wu-Cheng Kuo, Tzu-Han Lin
  • Publication number: 20130141917
    Abstract: The present invention provides an LED light device, including: a heat sink having a layered structure formed by a plurality of tubes; and a sub-mount positioned on the heat sink and mounted with an LED emitter.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Inventors: Tzy-Ying Lin, Wei-Ping Lin, I-Liang Huang, Jin-Lung Yang, Chung-Yu Yang, Tzu-Han Lin
  • Patent number: 8399969
    Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: March 19, 2013
    Assignee: VisEra Technologies Company Limited
    Inventors: Kuo-Ching Chang, Wu-Cheng Kuo, Tzu-Han Lin
  • Publication number: 20120205695
    Abstract: A light-emitting diode device is provided, including a submount, a light-emitting diode (LED) chip mounted on the submount, a first transparent insulating layer formed on the submount and the LED chip, a transparent conductive layer formed on the first transparent insulating layer, a phosphor layer formed on the first transparent conductive layer covering the LED chip, and a transparent passivation layer formed on the phosphor layer and over the transparent conductive layer.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 16, 2012
    Inventors: Tzu-Han Lin, Izy-Ying Lin, Ming-Nan Lin
  • Patent number: 8153458
    Abstract: Image sensing devices and methods for fabricating the same are provided. An exemplary image sensing device comprises a first substrate having a first side and a second side opposing each other. A plurality of image sensing elements is formed in the first substrate at the first side. A conductive via is formed through the first substrate, having a first surface exposed by the first substrate at the first side and a second surface exposed by the first substrate at the second side. A conductive pad overlies the conductive via at the first side and is electrically connecting the image sensing elements. A conductive layer overlies the conductive via at the second side and electrically connects with the conductive pad. A conductive bump is formed over a portion of the conductive layer. A second substrate is bonded with the first substrate at the first side.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: April 10, 2012
    Assignee: Visera Technologies Company Limited
    Inventors: Jui-Ping Weng, Tzu-Han Lin, Pai-Chun Peter Zung
  • Publication number: 20120025387
    Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 2, 2012
    Inventors: Kuo-Ching CHANG, Wu-Cheng Kuo, Tzu-Han Lin
  • Patent number: 7994598
    Abstract: An electronic assembly for an image sensor device is disclosed. The electronic assembly comprises a package module and a lens set mounted thereon. The package module comprises a device substrate comprising at least one grounding plug therein, in which the grounding plug is insulated from the device substrate and an array of optoelectronic devices therein. A transparent substrate comprises a dam portion attached to the device substrate to form a cavity between the device and transparent substrates. A micro-lens array is disposed within the cavity. A conductive layer is electrically connected to the grounding plug and covers the sidewalls of the lens set and the package module and the upper surface of the lens set. A method for fabricating the electronic assembly is also disclosed.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: August 9, 2011
    Assignee: Visera Technologies Company Limited
    Inventors: Jui-Ping Weng, Tzu-Han Lin