Patents by Inventor Tzu-Heng Chang
Tzu-Heng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200381419Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: Tzu-Heng CHANG, Jen-Chou TSENG, Ming-Hsiang SONG
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Publication number: 20200365579Abstract: A device includes first and second standard cells in a layout of an integrated circuit, and first and second active regions. The first standard cell includes an electrostatic discharge (ESD) protection unit, and the second standard cell includes first and second transistors that connect to the ESD protection unit. The first active region includes first, second, and third source/drain regions. The first standard cell includes a first gate arranged across the first active region; and a second gate that is separated from the first gate and is arranged across the first active region and the second active region. The first gate, the first source/drain region and the second source/drain region together correspond to a third transistor of the ESD protection unit. The second gate, the second source/drain region and the third source/drain region together correspond to the first transistor.Type: ApplicationFiled: August 6, 2020Publication date: November 19, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Heng CHANG, Kuo-Ji CHEN, Ming-Hsiang SONG
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Publication number: 20200365580Abstract: A device includes standard cells in a layout of an integrated circuit, the standard cells includes first and second standard cells sharing a first active region and a second active region. The first standard cell includes first and second gates. The first gate includes a first gate finger and a second gate finger that are arranged over the first active region, for forming the first transistor and the second transistor. The second gate is separate from the first gate, the second gate includes a third gate finger and a fourth gate finger that are arranged over the second active region, for forming the third transistor and the fourth transistor. The second standard cell includes a third gate arranged over the first active region and the second active region, for forming the fifth transistor and the sixth transistor. The first to fourth transistors operate as an electrostatic discharge protection circuit.Type: ApplicationFiled: August 6, 2020Publication date: November 19, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Heng CHANG, Kuo-Ji CHEN, Ming-Hsiang SONG
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Patent number: 10840237Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.Type: GrantFiled: February 9, 2018Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Fu Tsai, Tzu-Heng Chang, Yu-Ti Su, Kai-Ping Huang
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Patent number: 10756082Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.Type: GrantFiled: June 17, 2019Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
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Patent number: 10741543Abstract: A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.Type: GrantFiled: August 20, 2018Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Heng Chang, Kuo-Ji Chen, Ming-Hsiang Song
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Publication number: 20200219868Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.Type: ApplicationFiled: March 13, 2020Publication date: July 9, 2020Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
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Patent number: 10629588Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.Type: GrantFiled: November 28, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
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Publication number: 20190304967Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.Type: ApplicationFiled: June 17, 2019Publication date: October 3, 2019Inventors: Tzu-Heng CHANG, Jen-Chou TSENG, Ming-Hsiang SONG
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Patent number: 10325906Abstract: An electrostatic discharge (ESD) testing structure includes a measurement device in a first die. The ESD testing structure further includes a fuse in a second die. The ESD testing structure further includes a plurality of bonds electrically connecting the first die to the second die, wherein a first bond of the plurality of bonds electrically connects the fuse to the measurement device.Type: GrantFiled: September 23, 2016Date of Patent: June 18, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
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Publication number: 20190164952Abstract: A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.Type: ApplicationFiled: August 20, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Heng CHANG, Kuo-Ji CHEN, Ming-Hsiang SONG
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Patent number: 10284190Abstract: A voltage detector includes a first node configured to have a first supply voltage, a second node configured to have a second supply voltage, and an output node. The voltage detector is configured to drive the output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value.Type: GrantFiled: March 6, 2017Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Fu Tsai, Jen-Chou Tseng, Kuo-Ji Chen, Tzu-Heng Chang
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Publication number: 20190123001Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Jen-Chou Tseng, Tzu-Heng Chang
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Publication number: 20190109129Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.Type: ApplicationFiled: November 28, 2018Publication date: April 11, 2019Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
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Patent number: 10170461Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.Type: GrantFiled: September 21, 2016Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
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Publication number: 20180374839Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.Type: ApplicationFiled: February 9, 2018Publication date: December 27, 2018Inventors: Ming-Fu TSAI, Tzu-Heng CHANG, Yu-Ti SU, Kai-Ping HUANG
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Patent number: 10163823Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.Type: GrantFiled: April 8, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chou Tseng, Tzu-Heng Chang
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Patent number: 9979186Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, and an ESD detection circuit coupled to the common trigger line and to a first power line common to the other dies, wherein when the ESD detection circuit of one of the plural dies detects an ESD event, the ESD detection circuit is configured to generate a control signal to the common trigger line to control a power clamp in each of the plural dies to clamp an ESD event to the common first power line or a second power line.Type: GrantFiled: October 23, 2015Date of Patent: May 22, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
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Publication number: 20180088163Abstract: An electrostatic discharge (ESD) testing structure includes a measurement device in a first die. The ESD testing structure further includes a fuse in a second die. The ESD testing structure further includes a plurality of bonds electrically connecting the first die to the second die, wherein a first bond of the plurality of bonds electrically connects the fuse to the measurement device.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Inventors: Tzu-Heng CHANG, Jen-Chou TSENG, Ming-Hsiang SONG
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Patent number: 9842833Abstract: A chip includes a first die, a second die, a first and a second through-silicon vias, a first protection circuit, and a second protection circuit. The first die has a first operational voltage node and a first reference voltage node. The second die has a second operational voltage node and a second reference voltage node. The first and the second through-silicon vias are configured to couple the first die and the second die. The first protection circuit is coupled between the first operational voltage node and the first through-silicon via. The second protection circuit is coupled between the first reference voltage node and the second through-silicon via. The first through-silicon via is further coupled to the second reference voltage node or the second operational voltage node. The second through-silicon via is further coupled to the first reference voltage node or the first operational voltage node.Type: GrantFiled: April 15, 2014Date of Patent: December 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jen-Chou Tseng, Tzu-Heng Chang, Ming-Hsiang Song