Patents by Inventor Tzu-Hsiang Wang

Tzu-Hsiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20200292157
    Abstract: A light-emitting device including a substrate with a top surface and a bottom surface opposite to the top surface and a plurality of LED chips disposed on the top surface and configured to generate a top light visible above the top surface and a bottom light visible beneath the bottom surface, each LED chip comprising a plurality of light-emitting surfaces. The substrate has a thickness greater than 200 ?m and comprises aluminum oxide, sapphire, glass, plastic, or rubber. The plurality of LED chips has an incident light with a wavelength of 420-470 nm. The top light and the bottom light have a color temperature difference of not greater than 1500K.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Inventors: CHI-CHIH PU, CHEN-HONG LEE, SHIH-YU YEH, WEI-KANG CHENG, SHYI-MING PAN, SIANG-FU HONG, CHIH-SHU HUANG, TZU-HSIANG WANG, SHIH-CHIEH TANG, CHENG-KUANG YANG
  • Publication number: 20200243478
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Application
    Filed: August 27, 2019
    Publication date: July 30, 2020
    Applicant: EPISTAR CORPORATION
    Inventors: Min-Hsun HSIEH, Shih-An LIAO, Ying-Yang SU, Hsin-Mao LIU, Tzu-Hsiang WANG, Chi-Chih PU
  • Publication number: 20200243737
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 30, 2020
    Applicant: EPISTAR CORPORATION
    Inventors: Min-Hsun HSIEH, Shih-An LIAO, Ying-Yang SU, Hsin-Mao LIU, Tzu-Hsiang WANG, Chi-Chih PU
  • Publication number: 20200243582
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Inventors: SHENG-CHAN LI, I-NAN CHEN, TZU-HSIANG CHEN, YU-JEN WANG, YEN-TING CHIANG, CHENG-HSIEN CHOU, CHENG-YUAN TSAI
  • Patent number: 10725486
    Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: July 28, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yong-Ren Fang, Shen-Iuan Liu, Ju-Lin Huang, Tzu-Chien Tzeng, Keko-Chun Liang, Yu-Hsiang Wang, Che-Wei Yeh
  • Publication number: 20200226928
    Abstract: A vehicle information distributing method is provided, including: receiving a plurality of first vehicle information from a first base station to determine a first service area; receiving a plurality of second vehicle information from a second base station to determine a second service area; calculating a forwarding area based on a distance or an intersection between the first service area and the second service area; transferring the first vehicle information within the forwarding area to the second base station, and transferring the second vehicle information within the forwarding area to the first base station; and broadcasting, by the first base station, the second vehicle information from the forwarding area, and broadcasting, by the second base station, the first vehicle information from the forwarding area.
    Type: Application
    Filed: April 10, 2019
    Publication date: July 16, 2020
    Inventors: Kuo-Huang Hsu, Tzu-Hsiang Su, Yu-Che Wang, Yu-Dai Yan
  • Publication number: 20200197719
    Abstract: A light-emitting module includes a housing, a flexible film, and a protection portion. The housing includes a plurality of light-emitting units arranged in a matrix configuration and at least a switch electrically connected to at least one of the plurality of light-emitting units. The flexible film is detachably coupled to the housing. The protection portion covers the plurality of light-emitting units.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 25, 2020
    Inventors: Min-Hsun HSIEH, Jai-Tai KUO, Chang-Hseih WU, Tzu-Hsiang WANG, Chi-Chih PU
  • Publication number: 20200185597
    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Kun-Ju Li, Hsin-Jung Liu, I-Ming Tseng, Chau-Chung Hou, Yu-Lung Shih, Fu-Chun Hsiao, Hui-Lin Wang, Tzu-Hsiang Hung, Chih-Yueh Li, Ang Chan, Jing-Yin Jhang
  • Patent number: 10670244
    Abstract: The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 2, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chi-Chih Pu, Chen-Hong Lee, Shih-Yu Yeh, Wei-Kang Cheng, Shyi-Ming Pan, Siang-Fu Hong, Chih-Shu Huang, Tzu-Hsiang Wang, Shih-Chieh Tang, Cheng-Kuang Yang
  • Publication number: 20200158646
    Abstract: A surface-enhanced Raman scattering (SERS) detection method is provided for detecting a target analyte in a sample. The SERS detection method generally includes the steps of: (a). preparing an extract of the sample; (b). introducing the sample extract onto a SERS substrate, causing the target analyte to be absorbed in the SERS substrate; (c). introducing a volatile organic solvent onto the SERS substrate to have the target analyte of the sample extract dissolved and comes out of the SERS substrate; (d). irradiating the SERS substrate with light to evaporate the volatile organic solvent, leaving a more condensed target analyte on the SERS substrate; (e). irradiating the condensed target analyte with laser light to have the target analyte penetrate deeply into the SERS substrate; and (f). performing Raman measurement with a laser beam focusing on the SERS substrate to analyze the target analyte.
    Type: Application
    Filed: July 20, 2017
    Publication date: May 21, 2020
    Inventors: CHAO-MING TSEN, CHING-WEI YU, WEI-CHUNG CHAO, YUNG-HSIANG WANG, CHENG-CHIEN LI, SHAO-KAI LIN, TZU-HUNG HSU, CHANG-JUNG WEN
  • Patent number: 10658409
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. U.
    Inventors: Sheng-Chan Li, I-Nan Chen, Tzu-Hsiang Chen, Yu-Jen Wang, Yen-Ting Chiang, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 10596388
    Abstract: A light-emitting module includes a carrier, a plurality of light-emitting units, and a protection layer. The carrier has a lighting portion and an extending portion. The plurality of light-emitting units is disposed on the lighting portion. The protection layer covers the plurality of light-emitting units and the lighting portion, and exposes the extending portion.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: March 24, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Jai-Tai Kuo, Chang-Hseih Wu, Tzu-Hsiang Wang, Chi-Chih Pu
  • Publication number: 20200061941
    Abstract: The present disclosure provides a measurement method for a molding system comprising an upper mold and a lower mold forming a mold cavity. The method includes applying a pressure difference to a molding resin for driving the molding resin to flow into a preform in the mold cavity; detecting a flow front of the molding resin at a first position and a second position in the mold cavity; and calculating a flowing property of the molding resin based on the first position, the second position, a travelling time of the flow front from the first position to the second position, and the pressure difference.
    Type: Application
    Filed: October 29, 2019
    Publication date: February 27, 2020
    Inventors: Yuan YAO, Tzu-Heng CHIU, Rong-Yeu CHANG, Chia-Hsiang HSU, Chih-Wei WANG, Shih-Po SUN, Sung-Wei HUANG, Hsun YANG, Tsai-Heng TSAI
  • Patent number: 10553563
    Abstract: An electronic device includes a top carrier having a first top surface and a first bottom surface, a first electronic element formed on the first top surface, a second electronic element formed on the first bottom surface, a bottom carrier below the top carrier and having a second top surface near the top carrier, and a controller formed on the second top surface.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 4, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Jai-Tai Kuo, Chang-Hsieh Wu, Tzu-Hsiang Wang, Chi-Chih Pu, Ya-Wen Lin, Pei-Yu Li
  • Publication number: 20190371764
    Abstract: An electronic device includes a top carrier having a first top surface and a first bottom surface, a first electronic element formed on the first top surface, a second electronic element formed on the first bottom surface, a bottom carrier below the top carrier and having a second top surface near the top carrier, and a controller formed on the second top surface.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Inventors: Min-Hsun HSIEH, Jai-Tai KUO, Chang-Hsieh WU, Tzu-Hsiang WANG, Chi-Chih PU, Ya-Wen LIN, Pei-Yu LI
  • Publication number: 20190336439
    Abstract: The present disclosure relates generally to depot formulations of lurasidone and methods of making depot formulations of lurasidone. The depot formulations include a suspending agent and are highly syringeable.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 7, 2019
    Inventors: Chung-Chiang Hsu, Tzu-Ying WU, Wei-Hsiang Wang, Chia-Yu Kuo
  • Publication number: 20190304984
    Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Chun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Wei-Yang Lee, Tzu-Hsiang Hsu
  • Publication number: 20190252585
    Abstract: The application discloses a light-emitting device including a carrier, a light-emitting element and a connecting structure. The carrier includes a first connecting portion and a first necking portion extended from the first connecting portion. The first connecting portion has a first width, and the first necking portion has a second width. The second width is less than the first width. The light-emitting element includes a first light-emitting layer being able to emit a first light and a first contacting electrode formed under the first light-emitting layer. The first contacting electrode is corresponded to the first connecting portion. The connecting structure includes a first electrical connecting portion and a protection portion surrounding the first electrical connecting portion. The first electrical connecting portion is electrically connected to the first connecting portion and the first contacting electrode.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 15, 2019
    Inventors: Min-Hsun HSIEH, Tzu-Hsiang WANG
  • Patent number: D894851
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 1, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Tzu-Hsiang Wang, Chi-Chih Pu, Ya-Wen Lin