Abstract: A resin composition includes 100 parts by weight of hydrocarbon resin polymers and 0.01 to 50 parts by weight of divinyl aromatic compound. A substrate structure includes a resin layer and a conductive layer disposed on the resin layer, wherein the resin layer is formed from the resin composition. A manufacturing method of the resin composition includes the following steps: providing a mixture, wherein the mixture includes a monovinyl aromatic compound and a divinyl aromatic compound, and optionally includes a bridged ring compound; polymerizing the mixture to form a crude composition; and purifying the crude composition to prepare the resin composition.

Abstract: A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a graphene material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.

Abstract: A semiconductor device with a barrier layer between a gate structure and gate spacer layers, and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, performing a nitridation operation to form a barrier layer on the polysilicon structure and the fin structure, forming gate spacer layers on the barrier layer, forming a source/drain region in the fin structure and adjacent to the barrier layer, annealing the gate spacer layers, and replacing the polysilicon structure with a gate structure.

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a first side and a second side opposing the first side. The substrate has one or more sidewalls defining a trench extending along opposing sides of a pixel region having a first width. An isolation structure including one or more dielectric materials is disposed within the trench. The isolation structure has a second width. An image sensing element and a focal region are disposed within the pixel region. The focal region is configured to receive incident radiation along the second side of the substrate. A ratio of the second width to the first width is in a range of between approximately 0.1 and approximately 0.2, so that the focal region is completely confined between interior sidewall of the isolation structure facing the image sensing element.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device including a shallow trench isolation (STI) structure disposed between a first side and a second side of the semiconductor substrate. An intermetal dielectric structure comprising a first metal interconnect is on the second side. A first etching process is performed to form a first trench extending from the first side of the semiconductor substrate to the STI structure. An etch stop layer is deposited on the first side. A dielectric material is deposited into the first trench to form a dielectric spacer. A second trench is etched during a second etching process. The second trench is aligned with the first trench and extends through the STI structure to the first metal interconnect. A conductive material is deposited into the second trench to form a contact pad that contacts the first metal interconnect.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a first side and a second side opposing the first side. The substrate has one or more sidewalls defining a trench extending along opposing sides of a pixel region having a first width. An isolation structure including one or more dielectric materials is disposed within the trench. The isolation structure has a second width. An image sensing element and a focal region are disposed within the pixel region. The focal region is configured to receive incident radiation along the second side of the substrate. A ratio of the second width to the first width is in a range of between approximately 0.1 and approximately 0.2, so that the focal region is completely confined between interior sidewall of the isolation structure facing the image sensing element.

Abstract: An example compute cabinet assembly includes an equipment room, an air inlet channel coupled to the equipment room, and a cabinet fan module coupled to the equipment room. The compute cabinet assembly further includes first and second air outlet channels. The first air outlet channel extends along a side of the equipment room towards an outlet of the first air outlet channel. The second air outlet channel extends along another side of the equipment room towards an outlet of the second air outlet channel. The compute cabinet assembly also includes electric fans positioned in the cabinet fan module. The electric fans are configured to create airflow originating at an inlet of the air inlet channel, extending through the equipment room and cabinet fan module, and exiting the compute cabinet assembly at the outlets of the first and second air outlet channels.

Abstract: An example assembly includes an equipment room, a cabinet fan module having fans, and a processor configured to execute logic. Temperature sensors are positioned in the air inlet channel and the equipment room. An electrical component having an air inlet area is also positioned in the equipment room. The logic causes the fans to operate at a predetermined speed, and compare a temperature in the air inlet channel with a temperature at the air inlet area. In response to determining that the temperature at the air inlet area is greater than the temperature in the air inlet channel plus a constant value, the operating speed of the fans is increased. Moreover, the operating speed of the fans is decreased in response to determining that the ambient temperature in the air inlet channel plus a constant value is greater than or equal to the temperature at the air inlet area.

Abstract: An example compute cabinet assembly includes an equipment room configured to implement electrical components therein, an air inlet channel coupled to a first side of the equipment room, and a cabinet fan module coupled to a second side of the equipment room opposite the first side. A first air outlet channel is coupled to the cabinet fan module and extends along a third side of the equipment room towards a first outlet of the first air outlet channel. Moreover, electric fans are positioned in the cabinet fan module, the electric fans being configured to create an airflow path originating at an inlet of the air inlet channel. The airflow path further extends through the equipment room and cabinet fan module. A guide plate is also positioned adjacent to an inlet of the equipment room, the guide plate being configured to uniformly distribute the airflow path through the equipment room.

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.

Abstract: An image sensor device and methods of forming an image sensor device are provided. The image sensor device includes a plurality of image-sensing elements arranged within the device substrate. The image sensor device further includes an isolation grid structure extending into the device substrate and made up of a plurality of isolation grid segments that surround the outer perimeters of the plurality of image-sensing elements. The isolation grid structure includes a passivation liner and a conductive material in contact with the passivation liner. The conductive material may be an indium-tin-oxide film.

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

Abstract: Some implementations described herein provide for techniques to form a biased backside deep trench isolation and grid structure for a backside illumination image sensor. The techniques include forming an array of backside deep trench isolation structures and a biasing-pad that electrically connects to the array of metal-filled backside deep trench isolation structures through the grid structure. The array of backside deep trench isolation structures, the grid structure, and the biasing-pad structure may reduce a likelihood of electrical cross-talk and/or oblique light cross-talk between the photodiodes of the backside illumination image sensor. In this way, a performance of the backside illumination image sensor may be improved. Such improvements may include a suppression of a dark current within the backside illumination image sensor, a reduction in a number of white pixels, and a reduction in cross-talk within the backside illumination image sensor.

Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

Abstract: An optical structure and methods of forming an optical structure are provided. In some embodiments, the optical structure includes a substrate having a frontside and a backside opposite the frontside, a plurality of image-sensing elements arranged within the substrate, and a deep trench isolation (DTI) structure disposed between adjacent image-sensing elements. The DTI structure extends from the backside of the substrate to a first depth within the substrate and laterally surrounds the plurality of image-sensing elements. The optical structure further includes a light transmission layer formed over the backside of the substrate. The light transmission layer includes a first side and a second side adjacent to the backside of the substrate. The optical structure further includes a buried grid structure in the light transmission layer, the buried grid structure extending from the first side of the light transmission layer to a second depth within the light transmission layer.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first chip bonded to a second chip. The first chip includes a semiconductor substrate. The first chip includes a first transistor cell and a second transistor cell. The second transistor cell is laterally spaced from the first transistor cell. A first through-substrate via (TSV) extends vertically through the semiconductor substrate. The first transistor cell is electrically coupled to the first TSV. A second TSV extends vertically through the first semiconductor substrate. The second transistor cell is electrically coupled to the second TSV. The second chip comprises a first readout circuit that is electrically coupled to the first TSV and the second TSV. The first readout circuit is disposed laterally between the first TSV and the second TSV. The first readout circuit is configured to receive a first signal from the first transistor cell.