Abstract: A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

Abstract: A cooling device for a computing system is disclosed. The cooling device includes an inlet conduit, a first cold plate, a connecting conduit, a second cold plate, an outlet conduit, and a heat conductor. Coolant flows through the inlet conduit. The first cold plate has a first inlet surface and a first outlet surface. The inlet conduit is coupled to the first inlet surface. The inlet conduit transfers the coolant into the first cold plate. The connecting conduit is coupled at one end to the first outlet surface. The coolant flows from the first cold plate through the connecting conduit. The second cold plate has a second inlet surface and a second outlet surface, the connecting conduit being coupled at another end to the second inlet surface. The outlet conduit is coupled to the second outlet surface. The coolant flows from the second cold plate through the outlet conduit.

Abstract: A cooling system for a rack of servers includes a plurality of cooling circuits, where each cooling circuit is coupled to a server of the rack. Each cooling circuit includes a plurality of cooling modules arranged in parallel. Each cooling module includes a cold plate having a cooling conduit passing therethrough, and a pump fluidly coupled to the cooling conduit. The cooling circuit further includes one or more valves fluidly interconnecting the plurality of cooling modules. Each of the one or more valves, when turned on, fluidly connects the cooling conduits of any two adjacent cooling modules. The cooling system further includes a first cooling distribution manifold fluidly connected to the cooling circuit of each of the plurality of servers through an inlet pipe, and a second cooling distribution manifold fluidly connected to the cooling circuit of each of the plurality of servers through an outlet pipe.

Abstract: A cooling device for a computing system is disclosed. The cooling device includes an inlet conduit, a first cold plate, a connecting conduit, a second cold plate, an outlet conduit, and a heat conductor. Coolant flows through the inlet conduit. The first cold plate has a first inlet surface and a first outlet surface. The inlet conduit is coupled to the first inlet surface. The inlet conduit transfers the coolant into the first cold plate. The connecting conduit is coupled at one end to the first outlet surface. The coolant flows from the first cold plate through the connecting conduit. The second cold plate has a second inlet surface and a second outlet surface, the connecting conduit being coupled at another end to the second inlet surface. The outlet conduit is coupled to the second outlet surface. The coolant flows from the second cold plate through the outlet conduit.

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

Abstract: A computing device includes a sealed computer chassis housing, a heat source, a heat spreader, and a thermal pad. The sealed computer chassis housing, defines an interior space and an exterior surface with a heat sink for the interior space. The heat source is disposed within the interior space. The heat spreader includes a plurality of thermally-conductive protrusions coupled to one or more components of the heat source by an intermediate thermally conductive layer. The thermal pad is positioned above and in thermal contact with the heat spreader. The thermal pad is positioned to contact an interior wall of the sealed computer chassis housing opposite to the heat sink.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a first side and a second side opposing the first side. The substrate has one or more sidewalls defining a trench extending along opposing sides of a pixel region having a first width. An isolation structure including one or more dielectric materials is disposed within the trench. The isolation structure has a second width. An image sensing element and a focal region are disposed within the pixel region. The focal region is configured to receive incident radiation along the second side of the substrate. A ratio of the second width to the first width is in a range of between approximately 0.1 and approximately 0.2, so that the focal region is completely confined between interior sidewall of the isolation structure facing the image sensing element.

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the first portion and the second portion of the gate electrode.

Abstract: A method for performing an operation in a memory device is provided. The method includes the following steps. An erasing operation is performed on one selected word line of the memory device to ensure that a plurality of first cells to be programed and a plurality of second cells to be erased connected to the selected word line have threshold voltages lower than a first predetermined level. A programming operation is performed on the selected word line, such that the first cells are suffered a first program bias and the second cells are suffered a second program bias which is lower than the first program bias.

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

Abstract: A computing device includes a sealed computer chassis housing, a heat source, a heat spreader, and a thermal pad. The sealed computer chassis housing, defines an interior space and an exterior surface with a heat sink for the interior space. The heat source is disposed within the interior space. The heat spreader includes a plurality of thermally-conductive protrusions coupled to one or more components of the heat source by an intermediate thermally conductive layer. The thermal pad is positioned above and in thermal contact with the heat spreader. The thermal pad is positioned to contact an interior wall of the sealed computer chassis housing opposite to the heat sink.

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

Abstract: An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.

Abstract: A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.

Abstract: According to one example, a device includes a semiconductor substrate. The device further includes a plurality of color filters disposed above the semiconductor substrate. The device further includes a plurality of micro-lenses disposed above the set of color filters. The device further includes a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses. The structure and the color filters are level at respective top surfaces and bottom surfaces thereof.

Abstract: A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.