Abstract: The present disclosure provides a matrix device and an operation method thereof. The matrix device includes a transpose circuit and a memory. The transpose circuit is configured to receive a first element string representing a native matrix from a matrix source, wherein all elements in the native matrix are arranged in the first element string in one of a “row-major manner” and a “column-major manner”. The transpose circuit transposes the first element string into a second element string, wherein the second element string is equivalent to an element string in which all elements of the native matrix are arranged in another one of the “row-major manner” and the “column-major manner”. The memory is coupled to the transpose circuit to receive the second element string.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: The disclosure provides a look-up table (LUT) compression method and a LUT reading method for computation equipment and its host and device. In a LUT compression phase, the host retrieves an original data from an original LUT by using an original table address, checks the original data according to a reconstruction condition to obtain a check result (bitmap), converts the original data into a reconstructed data according to the check result, writes the reconstructed data to a compressed LUT by using a compressed table address, writes a relationship among the original table address, the compressed table address, and the check result (bitmap) to a mapping table, and stores the compressed LUT to the device.

Abstract: Frame running time of a device is estimated dynamically. The device includes a processor that executes threads of an application, and a graphics processor that receives commands from the processor for rendering frames. For each frame, the processor records a timer period for each thread in a set of threads that contribute to operations of a render thread. The render thread writes the commands for the graphics processor to render the frames. Each thread in the set of threads has a corresponding timer that controls a sleep state of the thread. The processor calculates a frame non-running time for a current frame using recorded one or more timer periods, and calculates the frame running time for the current frame by subtracting the frame non-running time from an end-to-end frame period.

Abstract: A method for performing processor resource allocation in an electronic device is provided, where the method may include the steps of: obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task (e.g. the heavy task may correspond to heavier loading than others of the plurality of tasks), to selectively utilize a specific processor core within a plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks. An apparatus for performing processor resource allocation according to the above method is provided.

Abstract: A multi-core processor system and method are provided. The multi-core processor system includes a plurality of processor cores and a task scheduler. The processor cores perform a plurality of tasks, wherein each of the tasks is in a respective one of a plurality of scheduling classes. The task scheduler obtains first task assignment information about tasks which are in a first scheduling class from the scheduling classes and assigned to the processor cores, obtains second task assignment information about tasks in one or more other scheduling classes and assigned to the processor cores, and refers to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores. Prior to the assigning the runnable task, the runnable task has been assigned to one of the processor cores.

Abstract: A multi-core processor system and a method for assigning tasks are provided. The multi-core processor system includes a plurality of processor cores, configured to perform a plurality of tasks, and each of the tasks is in a respective one of a plurality of scheduling classes. The multi-core processor system further includes a task scheduler, configured to obtain first task assignment information about tasks in a first scheduling class assigned to the processor cores, obtain second task assignment information about tasks in one or more other scheduling classes assigned to the processor cores, and refer to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores.

Abstract: A method for performing processor resource allocation in an electronic device is provided, where the method may include the steps of: obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task (e.g. the heavy task may correspond to heavier loading than others of the plurality of tasks), to selectively utilize a specific processor core within a plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks. An apparatus for performing processor resource allocation according to the above method is provided.

Abstract: A computing system with multiple processor cores manages power and performance by dynamic frequency scaling. The system detects a condition when a total number of active processor cores within one or more clusters is less than a predetermined number, and an operating frequency of the active processor cores has risen to a specified highest frequency. The system also obtains ambient temperature measurement of the one or more clusters. Upon detecting the condition, the system increases the operating frequency above the specified highest frequency based on the ambient temperature measurement while maintaining a same level of supply voltage to the active processor cores.

Abstract: A multi-core processor system and a method for assigning tasks are provided. The multi-core processor system includes a plurality of processor cores, configured to perform a plurality of tasks, and each of the tasks is in a respective one of a plurality of scheduling classes. The multi-core processor system further includes a task scheduler, configured to obtain first task assignment information about tasks in a first scheduling class assigned to the processor cores, obtain second task assignment information about tasks in one or more other scheduling classes assigned to the processor cores, and refer to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores.

Abstract: A task scheduling method for a multi-core processor system includes at least the following steps: when a first task belongs to a thread group currently in the multi-core processor system, where the thread group has a plurality of tasks sharing same specific data and/or accessing same specific memory address(es), and the tasks comprise the first task and at least one second task, determining a target processor core in the multi-core processor system based at least partly on distribution of the at least one second task in at least one run queue of at least one processor core in the multi-core processor system, and dispatching the first task to a run queue of the target processor core.

Abstract: A single flexible printed circuit (FPC) board for connecting multiple modules including a thin film is provided. The thin film has a first module connecting portion, a second module connecting portion and a third module connecting portion. The first module connecting portion is located on a first side of the thin film. The second module connecting portion and the third module connecting portion are located on a second side of the thin film. The first side is opposite to the second side. At least one first line is disposed between the first module connecting portion and the second module connecting portion. At least one second line is disposed between the first module connecting portion and the third module connecting portion.

Abstract: A single flexible printed circuit (FPC) board for connecting multiple modules including a thin film is provided. The thin film has a first module connecting portion, a second module connecting portion and a third module connecting portion. The first module connecting portion is located on a first side of the thin film. The second module connecting portion and the third module connecting portion are located on a second side of the thin film. The first side is opposite to the second side. At least one first line is disposed between the first module connecting portion and the second module connecting portion. At least one second line is disposed between the first module connecting portion and the third module connecting portion.

Abstract: A single flexible printed circuit (FPC) board for connecting multiple modules including a thin film is provided. The thin film has a first module connecting portion, a second module connecting portion and a third module connecting portion. The first module connecting portion is located on a first side of the thin film. The second module connecting portion and the third module connecting portion are located on a second side of the thin film. The first side is opposite to the second side. At least one first line is disposed between the first module connecting portion and the second module connecting portion. At least one second line is disposed between the first module connecting portion and the third module connecting portion.