Patents by Inventor Tzu-Jin Yeh
Tzu-Jin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9397729Abstract: Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.Type: GrantFiled: November 15, 2010Date of Patent: July 19, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Jin Yeh, Hsieh-Hung Hsieh, Jun-De Jin, Ming Hsien Tsai, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20160204191Abstract: A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Ta LU, Chi-Hsien LIN, Hsien-Yuan LIAO, Ho-Hsiang CHEN, Tzu-Jin YEH
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Publication number: 20160190127Abstract: A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the Schottky MOSFET. The source node of the enhancement MOSFET and source node of the Schottky MOSFET are connected together to form the power cell.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Inventors: Jun-De Jin, Tzu-Jin Yeh, Chewn-Pu Jou
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Patent number: 9374086Abstract: A method of electrically coupling a first node and a second node of a switch cell includes biasing the second node and a bias node of the switch cell at a direct current (DC) voltage level of a second voltage level greater than a first voltage level. A first switch unit coupled between the first node and the second node is tuned on by a first control signal having a third voltage level. The third voltage level being greater than the first voltage level, and a difference between the third voltage level and the first voltage level is about twice a difference between the second voltage level and the first voltage level. Also, a second switch unit coupled between the second node and the bias node is turned off by a second control signal having the first voltage level.Type: GrantFiled: November 9, 2012Date of Patent: June 21, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jun-De Jin, Ming Hsien Tsai, Tzu-Jin Yeh
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Patent number: 9355960Abstract: An electromagnetic bandgap (EBG) cell comprises a plurality of first conductive line layers beneath a first integrated circuit (IC) die, wherein wires on at least one of the first conductive line layers are each connected to one of a high voltage source and a low voltage source and are oriented to form a first mesh structure at a bottom of the EBG cell. The EBG cell further comprises a pair of through-substrate-vias (TSVs) above the plurality of first conductive line layers, wherein the pair of TSVs penetrate the first IC die and are connected to a high voltage source and a low voltage source, respectively, and a pair of micro bumps above a dielectric layer above the pair of TSVs, wherein the micro bumps connect the TSVs of the first IC die with a plurality of second conductive line layers formed on a second IC die.Type: GrantFiled: April 29, 2014Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung Hsieh, Tzu-Jin Yeh, Sa-Lly Liu, Tzong-Lin Wu
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Patent number: 9318487Abstract: A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell.Type: GrantFiled: July 9, 2013Date of Patent: April 19, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-De Jin, Tzu-Jin Yeh, Chewn-Pu Jou
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Patent number: 9293521Abstract: A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.Type: GrantFiled: August 8, 2014Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Ta Lu, Chi-Hsien Lin, Hsien-Yuan Liao, Ho-Hsiang Chen, Tzu-Jin Yeh
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Publication number: 20160043576Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.Type: ApplicationFiled: October 21, 2015Publication date: February 11, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jun-De JIN, Fan-Ming KUO, Huan-Neng CHEN, Ming-Hsien TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH
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Patent number: 9255963Abstract: A device comprises a radio frequency peak detector configured to receive an ac signal from a voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector and a feedback control unit coupled between an output of the radio frequency peak detector and an input of the voltage controlled oscillator.Type: GrantFiled: April 15, 2014Date of Patent: February 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsieh-Hung Hsieh, Ming Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20160013141Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Chia-Chung Chen, Chi-Feng Huang, Shu Fang Fu, Tzu-Jin Yeh, Chewn-Pu Jou
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Publication number: 20150364417Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Inventors: Chiao-Han LEE, Hsien-Yuan LIAO, Ying-Ta LU, Chi-Hsien LIN, Ho-Hsiang CHEN, Tzu-Jin YEH
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Patent number: 9177715Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.Type: GrantFiled: November 23, 2010Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-De Jin, Fan-Ming Kuo, Huan-Neng Chen, Ming Hsien Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh
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Patent number: 9178058Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.Type: GrantFiled: April 19, 2013Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Chi-Feng Huang, Shu Fang Fu, Tzu-Jin Yeh, Chewn-Pu Jou
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Publication number: 20150311159Abstract: An electromagnetic bandgap (EBG) cell comprises a plurality of first conductive line layers beneath a first integrated circuit (IC) die, wherein wires on at least one of the first conductive line layers are each connected to one of a high voltage source and a low voltage source and are oriented to form a first mesh structure at a bottom of the EBG cell. The EBG cell further comprises a pair of through-substrate-vias (TSVs) above the plurality of first conductive line layers, wherein the pair of TSVs penetrate the first IC die and are connected to a high voltage source and a low voltage source, respectively, and a pair of micro bumps above a dielectric layer above the pair of TSVs, wherein the micro bumps connect the TSVs of the first IC die with a plurality of second conductive line layers formed on a second IC die.Type: ApplicationFiled: April 29, 2014Publication date: October 29, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung Hsieh, Tzu-Jin Yeh, Sa-Lly Liu, Tzong-Lin Wu
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Patent number: 9129940Abstract: An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.Type: GrantFiled: March 14, 2012Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung Hsieh, Yi-Hsuan Liu, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20150249051Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.Type: ApplicationFiled: May 15, 2015Publication date: September 3, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming Hsien TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH, Chewn-Pu JOU, Sa-Lly LIU, Fu-Lung HSUEH
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Patent number: 9093977Abstract: The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology.Type: GrantFiled: July 31, 2012Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-De Jin, Ming Hsien Tsai, Tzu-Jin Yeh
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Patent number: 9071203Abstract: A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well.Type: GrantFiled: July 11, 2013Date of Patent: June 30, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Jin Yeh, Chewn-Pu Jou, Jun-De Jin, Hsieh-Hung Hsieh, Chia-Chung Chen
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Patent number: 9064631Abstract: A transformer for RF and other frequency through-chip-interface (TCI) applications includes multiple chips in wireless electronic communication with one another in three-dimensional integrated circuit, 3DIC, technology. Each of the chips includes an inductor coil and a matching network that matches the impedance of the inductor coil. The matching network is electrically coupled between the inductor coil and further components and circuits formed on the chip.Type: GrantFiled: January 13, 2012Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-De Jin, Tzu-Jin Yeh
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Patent number: 9048127Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.Type: GrantFiled: September 25, 2013Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsien Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Chewn-Pu Jou, Sa-Lly Liu, Fu-Lung Hsueh