Abstract: The present disclosure describes a semiconductor device that includes a first die bonded to a second die with interconnect structures in the first die. The first die includes a photodiode having first and second electrodes on a first side of a first dielectric layer, and first, second, and third interconnect structures in the first dielectric layer. The first and second interconnect structures are connected to the first and second electrodes, respectively. The second electrode has a polarity opposite to the first electrode. The second and third interconnect structures extend to a second side opposite to the first side of the first dielectric layer. The second die includes a second dielectric layer and a fourth interconnect structure in the second dielectric layer. The second dielectric layer is bonded to the second side of the first dielectric layer. The fourth interconnect structure connects the second and third interconnect structures.

Abstract: The problem of forming a deep trench isolation structure suitable for photodetectors with small pitch is solved by a process in which a grid of trenches is etched from the front side using high energy plasma followed by annealing. The trenches are filled with an oxide followed by etching to recess the oxide. The trench recesses are filled with semiconductor to form a grid-shaped semiconductor structure. After FEOL processing, BEOL processing, attachment to a second substrate, and thinning from the back side, an etch removes the oxide from the back side. The etch stops on the grid-shaped semiconductor structure. The trenches are then lined and filled from the back side. The front side etch allows the trenches to be made narrow and with highly vertical sidewalls. Lining and filling the trenches from the back side provides good optical and electrical isolation.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.

Abstract: In some embodiments, the present disclosure relates to an image sensor including a substrate having a first side and a second side opposite the first side; a photodetector region within the substrate; a gate structure on the first side of the substrate over the photodetector region; a deep trench isolation (DTI) structure surrounding the photodetector region and extending from the first side of the substrate to the second side; a doped floating node region within the substrate at the first side and disposed between the gate structure and the DTI structure; and a floating node on the first side of the substrate, contacting a top surface of the DTI structure and overlying the doped floating node region.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.

Abstract: The present disclosure relates to an image sensor including a pixel along a substrate. The pixel includes a first semiconductor region having a first doping type. A second semiconductor region is directly over the first semiconductor region. The second semiconductor region has a second doping type opposite the first doping type and meets the first semiconductor region at a p-n junction. A ring-shaped third semiconductor region laterally surrounds the first and second semiconductor regions. The ring-shaped third semiconductor region has the first doping type. A ring-shaped fourth semiconductor region laterally surrounds the ring-shaped third semiconductor region. The ring-shaped fourth semiconductor region has the second doping type. A ring-shaped fifth semiconductor region is directly over the ring-shaped third semiconductor region and has the second doping type.

Abstract: A photovoltaic cell includes a germanium-containing well embedded in a single crystalline silicon substrate and extending to a proximal horizontal surface of the single crystalline silicon substrate, wherein germanium-containing well includes germanium at an atomic percentage greater than 50%. A silicon-containing capping structure is located on a top surface of the germanium-containing well and includes silicon at an atomic percentage greater than 42%. The silicon-containing capping structure prevents oxidation of the germanium-containing well. A photovoltaic junction may be formed within, or across, the trench by implanting dopants of a first conductivity type and dopants of a second conductivity type.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first IC chip includes a plurality of photodetectors disposed in a first substrate and a first bond structure. The first bond structure includes a first plurality of bond contacts disposed on a first plurality of conductive bond pads. The second IC chip includes a second bond structure and a second substrate. A first bond interface is disposed between the first bond structure and the second bond structure. The second bond structure comprises a second plurality of bond contacts. The first bond structure further includes a first plurality of shield structures disposed between adjacent conductive bond pads in the first plurality of conductive bond pads.

Abstract: Various embodiments of the present disclosure relate to an interstitial stacked-integrated-circuit interface shielding structure. A first integrated circuit (IC) chip includes a first dielectric layer. A second IC chip is bonded to the first IC chip at a bond interface and includes a second dielectric layer directly contacting the first dielectric layer at the bond interface. A first pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. A second pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. A pair of shield structures are respectively in the first and second dielectric layers and directly contact at the bond interface. Further, the pair of shield structures separate the first pair of conductive pads from the second pair of conductive pads.

Abstract: Some embodiments relate to an IC device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.

Abstract: Some embodiments relate to an IC device, including a first chip; and a second chip bonded to the first chip at a bonding interface; where the first and second chips respectively comprise a first dielectric layer and a second dielectric layer directly contacting; the first chip further comprises a plurality of conductive pads recessed into the first dielectric layer and in a plurality of rows and columns; where the plurality of conductive pads are arranged with a zig-zag layout along the plurality of columns and along the plurality of rows and comprise a first conductive pad and a second conductive pad; the first chip further comprises a first shield line in the first dielectric layer and laterally between the first and second conductive pads, and the second chip further comprises a contact recessed into the second dielectric layer and directly contacting the first conductive pad at the bonding interface.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first chip IC includes a first bond structure. The first bond structure includes a first plurality of conductive bond pads and a first plurality of shield structures disposed between adjacent conductive bond pads among the first plurality of conductive bond pads. The second IC chip includes a second bond structure. A bonding interface is disposed between the first bond structure and the second bond structure. The second bond structure includes a second plurality of conductive bond pads and a second plurality of shield structures. The first plurality of conductive bond pads contacts the second plurality of conductive bond pads and the first plurality of shield structures contacts the second plurality of shield structures at the bonding interface.

Abstract: The present disclosure relates to an image sensor integrated chip structure. The image sensor integrated chip structure includes one or more logic devices disposed within a first substrate and coupled to a first interconnect structure on the first substrate. A plurality of pixel support devices are disposed along a first-side of a second substrate and coupled to a second interconnect structure on the second substrate. The first substrate is bonded to the second substrate. A plurality of image sensing elements are disposed within a third substrate in pixel regions respectively including two or more of the plurality of image sensing elements. A plurality of transfer gates and a third interconnect structure are disposed on a first-side of the third substrate. The third interconnect structure includes interconnect wires and vias confined between the first-side of second substrate and the first-side of the third substrate.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor comprising a pixel with a dual-PD layout for enhanced scaling down. The pixel spans a first integrated circuit (IC) die and a second IC die stacked with the first IC die. The pixel comprises a plurality of photodetectors in the first IC die, and further comprises a plurality of pixel transistors split amongst the first IC die and the second IC die. The plurality of photodetectors are grouped into one or more pairs, each having the dual-PD layout. A DTI structure completely and individually surrounds the plurality of photodetectors, and further extends completely through a substrate within which the plurality of photodetectors are arranged. As such, the DTI structure completely separates the plurality of photodetectors from each other.

Abstract: The present disclosure relates to an image sensor including a pixel along a substrate. The pixel includes a first semiconductor region having a first doping type. A second semiconductor region is directly over the first semiconductor region. The second semiconductor region has a second doping type opposite the first doping type and meets the first semiconductor region at a p-n junction. A ring-shaped third semiconductor region laterally surrounds the first and second semiconductor regions. The ring-shaped third semiconductor region has the first doping type. A ring-shaped fourth semiconductor region laterally surrounds the ring-shaped third semiconductor region. The ring-shaped fourth semiconductor region has the second doping type. A ring-shaped fifth semiconductor region is directly over the ring-shaped third semiconductor region and has the second doping type.

Abstract: A photovoltaic cell includes a germanium-containing well embedded in a single crystalline silicon substrate and extending to a proximal horizontal surface of the single crystalline silicon substrate, wherein germanium-containing well includes germanium at an atomic percentage greater than 50%. A silicon-containing capping structure is located on a top surface of the germanium-containing well and includes silicon at an atomic percentage greater than 42%. The silicon-containing capping structure prevents oxidation of the germanium-containing well. A photovoltaic junction may be formed within, or across, the trench by implanting dopants of a first conductivity type and dopants of a second conductivity type.

Abstract: An integrated chip including a first semiconductor substrate. The first semiconductor substrate includes a doped region. A first photodetector and a second photodetector are in the first semiconductor substrate. A trench isolation layer at least partially surrounds the first photodetector and the second photodetector and extends between the first photodetector and the second photodetector. The trench isolation layer has a first pair of sidewalls. The first semiconductor substrate extends from the first photodetector, between the first pair of sidewalls, to the second photodetector. The doped region is between the first pair of sidewalls. The first photodetector and a first gate partially form a first transistor. The second photodetector and a second gate partially form a second transistor. A second semiconductor substrate is over the first gate and the second gate. A third transistor is along the second semiconductor substrate. The third transistor is coupled to the first transistor.

Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.

Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.