Patents by Inventor Tzu-Wei Lin
Tzu-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250138593Abstract: A laptop computer including a first body, a circuit board disposed in the first body, a second body, a display module disposed in the second body, a hinge connected to the first and the second bodies, and a mezzanine connector is provided. The first and the second bodies are pivoted to each other to be folded or unfolded via the hinge. The mezzanine connector is clamped between the hinge and the circuit board, and is electrically connected between the display module and the circuit board.Type: ApplicationFiled: March 28, 2024Publication date: May 1, 2025Applicant: Acer IncorporatedInventors: Yu-Shih Wang, Wen-Chieh Tai, Chih-Chun Liu, Dong-Sheng Wu, Tzu-Wei Lin, Yi-Mu Chang
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Publication number: 20250138594Abstract: A laptop computer including a casing, an inner frame, and a plurality of electronic modules is provided. The inner frame is detachably assembled to the casing and forms a plurality of receiving zones separated from each other. The electronic modules are respectively disposed in the receiving zones and connected to each other via a plurality of flexible electrical conducting members, and the electrical conducting members pass through a recess structure of the inner frame.Type: ApplicationFiled: April 1, 2024Publication date: May 1, 2025Applicant: Acer IncorporatedInventors: Yu-Shih Wang, Wen-Chieh Tai, Chih-Chun Liu, Dong-Sheng Wu, Tzu-Wei Lin, Yi-Mu Chang
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Publication number: 20250138600Abstract: A laptop computer including a first casing, a first sub-circuit board, an input module, a second casing, a motherboard, and a bridge circuit board is provided. The first sub-circuit board is disposed at the first casing. The input module is disposed at the first casing and electrically connected to the first sub-circuit board. The motherboard is disposed at the second casing. The first casing and the second casing are assembled together, such that the first sub-circuit board, the bridge circuit board, and the motherboard are partially overlapped, and the first sub-circuit board is electrically connected to the motherboard via the bridge circuit board.Type: ApplicationFiled: April 1, 2024Publication date: May 1, 2025Applicant: Acer IncorporatedInventors: Yu-Shih Wang, Wen-Chieh Tai, Chih-Chun Liu, Dong-Sheng Wu, Tzu-Wei Lin, Yi-Mu Chang
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Publication number: 20250141142Abstract: A laptop computer including a circuit board, a connector, and a fan is provided. The circuit board has a plurality of first electrically conducting members. The connector has a body and a plurality of clamping terminals and pogo pin terminals extended from the body. The clamping terminals and the pogo pin terminals are electrically connected to each other and located at two opposite sides of the body. The clamping terminals clamp the circuit board and are electrically connected to the first electrically conductive members. The fan has a plurality of second electrically conducting members, and the pogo pin terminals are respectively abutted against abutting surfaces of the second electrically conducting members, such that the circuit board is electrically connected to the fan via the connector, wherein each of the abutting surfaces is tilted relative to a plane where the pogo pin terminals are arranged.Type: ApplicationFiled: April 1, 2024Publication date: May 1, 2025Applicant: Acer IncorporatedInventors: Yu-Shih Wang, Wen-Chieh Tai, Chih-Chun Liu, Dong-Sheng Wu, Tzu-Wei Lin, Yi-Mu Chang
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Patent number: 12222797Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: December 19, 2022Date of Patent: February 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: James Mossman, Robert Cohen, Sudherssen Kalaiselvan, Tzu-Wei Lin
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Publication number: 20240371867Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Inventors: Yi-Chen HO, Chien LIN, Tzu-Wei LIN, Ju Ru HSIEH, Ching-Lun LAI, Ming-Kai LO
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Publication number: 20240300211Abstract: A laminated composite component is provided in this disclosure. The laminated composite component comprises a foam material layer, a first laminated sheet group and a second laminated sheet group. The foam material layer has a first surface and a second surface opposite to each other. The first laminated sheet group is disposed on the first surface. The second laminated sheet group is disposed on the second surface. The first laminated sheet group includes a plurality of first sheets. The second laminated sheet group includes a plurality of second sheets. The foam material layer, the first sheets of the first laminated sheet group, and the second sheets of the second laminated sheet group are laminated and pressed to form in one piece.Type: ApplicationFiled: February 20, 2024Publication date: September 12, 2024Applicant: Acer IncorporatedInventors: Dong-Sheng WU, Tzu-Wei LIN, Chih-Chun LIU, Cheng-Nan LING, Wen-Chieh TAI
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Patent number: 12068317Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.Type: GrantFiled: April 22, 2022Date of Patent: August 20, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chen Ho, Chien Lin, Tzu-Wei Lin, Ju Ru Hsieh, Ching-Lun Lai, Ming-Kai Lo
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Patent number: 12039337Abstract: A processor employs a plurality of fetch and decode pipelines by dividing an instruction stream into instruction blocks with identified boundaries. The processor includes a branch predictor that generates branch predictions. Each branch prediction corresponds to a branch instruction and includes a prediction that the corresponding branch is to be taken or not taken. In addition, each branch prediction identifies both an end of the current branch prediction window and the start of another branch prediction window. Using these known boundaries, the processor provides different sequential fetch streams to different ones of the plurality of fetch and decode states, which concurrently process the instructions of the different fetch streams, thereby improving overall instruction throughput at the processor.Type: GrantFiled: September 25, 2020Date of Patent: July 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Robert B. Cohen, Tzu-Wei Lin, Anthony J. Bybell, Bill Kai Chiu Kwan, Frank C. Galloway
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Publication number: 20240201777Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: December 19, 2022Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventors: James Mossman, Robert Cohen, Sudherssen Kalaiselvan, Tzu-Wei Lin
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Patent number: 11953523Abstract: An analog front-end (AFE) circuit, configured to be coupled to a sensor having a plurality of sensing units, includes a plurality of sensing circuits and a plurality of multiplexers. Each of the plurality of multiplexers is coupled between one of the plurality of sensing units and at least two of the plurality of sensing circuits.Type: GrantFiled: November 30, 2021Date of Patent: April 9, 2024Assignee: NOVATEK Microelectronics Corp.Inventors: Tzu-Wei Lin, Hung-Kai Chen, Feng-Lin Chan
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Publication number: 20240068119Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.Type: ApplicationFiled: March 2, 2023Publication date: February 29, 2024Applicant: Acer IncorporatedInventors: Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
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Patent number: 11907126Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.Type: GrantFiled: December 9, 2020Date of Patent: February 20, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Robert B. Cohen, Tzu-Wei Lin, Anthony J. Bybell, Sudherssen Kalaiselvan, James Mossman
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Patent number: 11773205Abstract: The present disclosure provides a crosslinking agent, the preparation process and uses thereof, a hydrogel and a biodegradable cryogel including the crosslinking agent.Type: GrantFiled: August 20, 2020Date of Patent: October 3, 2023Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Shan-hui Hsu, Tzu-Wei Lin
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Patent number: 11775030Abstract: A portable electronic device includes a first body, a second body, a hinge mechanism, a spring, and a cable extending from the first body to the second body. The second body is connected to the first body through the hinge mechanism. The first body has a first pillar, a second pillar, and a third pillar. The second pillar is located between the first pillar and the third pillar. The spring is disposed in the first body as corresponding to the second pillar. The cable includes a first winding segment extending through a gap between the first pillar and the second pillar, a second winding segment extending through a gap between the second pillar and the spring, and a third winding segment extending through a gap between the second pillar and the third pillar. Two ends of the spring are respectively connected to the first body and the second winding segment.Type: GrantFiled: September 7, 2022Date of Patent: October 3, 2023Assignee: Acer IncorporatedInventors: Pao-Min Huang, Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
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Publication number: 20230168282Abstract: An analog front-end (AFE) circuit, configured to be coupled to a sensor having a plurality of sensing units, includes a plurality of sensing circuits and a plurality of multiplexers. Each of the plurality of multiplexers is coupled between one of the plurality of sensing units and at least two of the plurality of sensing circuits.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Applicant: NOVATEK Microelectronics Corp.Inventors: Tzu-Wei Lin, Hung-Kai Chen, Feng-Lin Chan
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Publication number: 20220413564Abstract: A portable electronic device includes a first body, a second body, a hinge mechanism, a spring, and a cable extending from the first body to the second body. The second body is connected to the first body through the hinge mechanism. The first body has a first pillar, a second pillar, and a third pillar. The second pillar is located between the first pillar and the third pillar. The spring is disposed in the first body as corresponding to the second pillar. The cable includes a first winding segment extending through a gap between the first pillar and the second pillar, a second winding segment extending through a gap between the second pillar and the spring, and a third winding segment extending through a gap between the second pillar and the third pillar. Two ends of the spring are respectively connected to the first body and the second winding segment.Type: ApplicationFiled: September 7, 2022Publication date: December 29, 2022Applicant: Acer IncorporatedInventors: Pao-Min Huang, Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
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Patent number: 11474569Abstract: A portable electronic device includes a first body, a second body, a hinge mechanism, a spring, and a cable extending from the first body to the second body. The second body is connected to the first body through the hinge mechanism. The first body has a first pillar, a second pillar, and a third pillar. The second pillar is located between the first pillar and the third pillar. The spring is disposed in the first body as corresponding to the second pillar. The cable includes a first winding segment extending through a gap between the first pillar and the second pillar, a second winding segment extending through a gap between the second pillar and the spring, and a third winding segment extending through a gap between the second pillar and the third pillar. Two ends of the spring are respectively connected to the first body and the second winding segment.Type: GrantFiled: June 23, 2021Date of Patent: October 18, 2022Assignee: Acer IncorporatedInventors: Pao-Min Huang, Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
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Publication number: 20220261033Abstract: A portable electronic apparatus includes a first body having a pivoting side and a heat dissipating hole located at the pivoting side, a second body, and a hinge mechanism. The second body is rotatably and slidably connected to the first body through the hinge mechanism including a rack fixed in the first body as corresponding to the pivoting side, a rotating shaft connected to the second body, and a driving component connected to the rotating shaft and mechanically coupled to the rack. When the second body rotates and unfolds with respect to the first body, the rotating shaft rotates together with the second body, the driving component rotates with the rotating shaft, and the driving component rotates and slides with respect to the rack and drives the second body to slide away from the pivoting side to increase a distance between the second body and the heat dissipating hole.Type: ApplicationFiled: September 17, 2021Publication date: August 18, 2022Applicant: Acer IncorporatedInventors: Tzu-Wei Lin, Pao-Min Huang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
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Publication number: 20220246609Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Inventors: Yi-Chen HO, Chien LIN, Tzu-Wei LIN, Ju Ru HSIEH, Ching-Lun LAI, Ming-Kai LO