Abstract: A semiconductor structure includes at least one sub-word line driver. The sub-word line driver includes a plurality of first active areas and a main-word line. The main-word line includes a plurality of first gates and a plurality of second gates interconnected. The plurality of first gates correspond to the plurality of first active areas. An extension direction of the plurality of first gates in the main-word line and/or an extension direction of at least part of the second gates in the main-word line intersects both a first direction and a second direction. The first direction is parallel to a direction in which the first active areas extend, and the second direction is parallel to a plane in which the first active areas are located and is perpendicular to the first direction.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a base is provided, in which the base includes a first doped area and a second doped area, and an isolation structure is provided between the first doped area and the second doped area; nitridation treatment is performed on the first doped area and the second doped area; and oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form a first gate oxide layer and a second gate oxide layer respectively.

Abstract: A semiconductor structure includes a storage chip, a control chip, and a capacitor structure. The storage chip includes an array area. The control chip includes a peripheral area. The control chip and the storage chip are connected in a face-to-face bonding manner. The capacitor structure is located on a surface, away from a bonding surface, of the storage chip. The capacitor structure includes capacitors electrically connected to corresponding transistors in the array area.

Abstract: A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a base is provided, in which the base includes a first doped area and a second doped area, and an isolation structure is provided between the first doped area and the second doped area; nitridation treatment is performed on the first doped area and the second doped area; and oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form a first gate oxide layer and a second gate oxide layer respectively.

Abstract: Provided are a semiconductor device, a method for manufacturing it and an application thereof. The semiconductor device includes a substrate; a semiconductor material layer located on the substrate and covering a part of the substrate; a gate located on the semiconductor material layer and the substrate not covered by the semiconductor material layer; in which, along an extending direction of the gate, a width of the semiconductor material layer is smaller than a width of the substrate, and a carrier mobility of a material of the semiconductor material layer is different from a carrier mobility of a material of the substrate.

Abstract: A semiconductor structure includes the following: a semiconductor substrate; a first metal layer, located on a surface of the semiconductor substrate; a second metal layer, located above a surface of the first metal layer; an insulating layer, located between the first metal layer and the second metal layer, and configured to isolate the first metal layer and the second metal layer; a test via, penetrating through the insulating layer and connecting the first metal layer with the second metal layer through a conductive material in the test via; and at least a pair of dummy vias, penetrating through the insulating layer and connected to any one of the first metal layer and the second metal layer.

Abstract: A semiconductor structure includes: a semiconductor substrate; a first metal layer located on a surface of the semiconductor substrate; a second metal layer located above a surface of the first metal layer; an insulating layer located between the first metal layer and the second metal layer and configured to isolate the first metal layer from the second metal layer; and at least four vias located in the insulating layer and a conductive material for connecting the first metal layer and the second metal layer is filled in the at least four vias.

Abstract: The present disclosure relates to a layout structure forming method of a sense amplifier and a layout structure of a sense amplifier. The method includes: providing a first active region layout structure layer, the first metal contact pattern layer includes a first metal contact pattern and a second metal contact pattern that are located on two opposite sides of the first pattern region; the first conductive wire pattern layer includes a first conductive wire pattern covering the first metal contact pattern and the second metal contact pattern; and the first connection hole pattern layer includes a plurality of connection hole designs, and the connection hole designs are connected to form a connection structure connected to the first metal contact pattern layer.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method includes providing a substrate, where the substrate includes a device region and a peripheral region; and forming a bit line structure in the device region, and forming a transistor structure in the peripheral region, where the transistor structure includes a gate structure, and the bit line structure includes a bit line conductive layer and a bit line protective layer; the gate structure includes a gate oxide layer, a high-k dielectric layer, a gate conductive layer and a gate protective layer; the gate conductive layer and the bit line conductive layer are obtained by patterning a same conductive material layer, and the bit line protective layer and the gate protective layer are obtained by patterning a same protective material layer.

Abstract: The present disclosure relates to a method of forming a sense amplifier and a layout structure of a sense amplifier. The method includes: providing a first active region pattern layer, the first active region pattern layer includes a bridge pattern, and a first active region pattern region and a second active region pattern region; the first active region pattern region includes a first active region pattern for defining a first pull-down transistor of a first memory cell structure; the second active region pattern region includes a first symmetrical active region pattern for defining a second pull-down transistor of a second memory cell structure; and the first active region pattern and the first symmetrical active region pattern are adjacent to each other and connected through the bridge pattern, a source of the first pull-down transistor and a source of the second pull-down transistor are electrically connected through the bridge pattern.

Abstract: A semiconductor structure includes a Through Silicon Via (TSV) and a protective ring disposed outside the TSV; the protective ring includes at least two protective layers arranged in parallel and surrounding the TSV; each of the protective layers includes a first protective structure and second protective structures disposed surrounding the first protective structure; the first protective structure is a polygonal structure; a number of sides of the polygonal structure is greater than or equal to 4; and the second protective structures are disposed on an inner side and an outer side of each corner area of the polygonal structure.

Abstract: A semiconductor structure including a semiconductor base and a test element group is provided. The test element group includes a first metal layer, a second metal layer, and a through-silicon via. The first metal layer is located on the semiconductor base. Reserved space running through the first metal layer is formed on the first metal layer. The second metal layer is located above the first metal layer and is spaced away from the first metal layer. The through-silicon via is located inside the semiconductor base and runs through the reserved space, and the through-silicon via is connected to the second metal layer. The cross-sectional area of the through-silicon via is less than the cross-sectional area of the reserved space, so that the through-silicon via is spaced away from the first metal layer.

Abstract: A semiconductor device and a method for manufacturing same are provided. A semiconductor device includes: an active area located in a semiconductor substrate and including a central area and a peripheral area surrounding the central area; a first strained layer formed in the peripheral area in an embedded manner, and including at least a first sub-portion, a second sub-portion, a third sub-portion, and a fourth sub-portion, where the first sub-portion and the third sub-portion are separately arranged on two sides of the central area in first direction, and the second sub-portion and the fourth sub-portion are separately arranged on the other two sides of the central area in second direction; and a gate located on the active area, extending in a first direction and covering at least a part of the central area, at least a part of the first sub-portion, and at least a part of the third sub-portion.

Abstract: Provided are a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes: a through silicon via and a shielding structure disposed at an outer side of the through silicon via, in which the shielding structure includes at least two non-closed annular shielding layers surrounding the through silicon via and at least one conductive plug configured to connect two adjacent ones of the non-closed annular shielding layers; the at least two non-closed annular shielding layers and the at least one conductive plug are alternately distributed along an extending direction of the through silicon via and sequentially connected to form a conductive path, and current flow directions in two adjacent ones of the non-closed annular shielding layers in the conductive path are opposite.

Abstract: A method for manufacturing a semiconductor structure, including: providing a base; forming a Through Silicon Via (TSV) in the base, with a depth of the TSV being less than a thickness of the base; and forming a liner layer on a sidewall and the bottom of the TSV, and forming a conductive layer in the TSV, the liner layer including a polish-stop layer.

Abstract: The present disclosure relates to a manufacturing method of a semiconductor structure, including: the base includes an array region and a peripheral region a depth of the TSV is smaller than a thickness of the base; forming a filling dielectric layer; forming a conductive layer in the TSV, the conductive layer is flush with an upper surface of the filling dielectric layer; forming first metal layers an upper surface of each of the first metal layers is flush with an upper surface of the conductive layer; forming a first dielectric layer; and forming a first interconnection structure and second interconnection structures at the same time in the first dielectric layer, a bottom of the first interconnection structure is in contact with one of the first metal layers, and bottoms of the second interconnection structures are in contact with the conductive layer.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The method includes: forming a laminated structure, wherein the laminated structure includes first dielectric layers and second dielectric layers laminated alternately and sequentially from bottom to top; forming a contact hole, wherein the contact hole penetrates the laminated structure at least in a thickness direction, and a width of a part, of the contact hole, in the second dielectric layer is greater than a width of a part, of the contact hole, in the adjacent first dielectric layer; and forming contact structure in the contact hole, wherein the contact structure fills up the contact hole.

Abstract: The present application discloses a graphic element structure and a graphic array structure. The graphic element structure includes a first graphic, a second graphic, and a third graphic, where the first graphic includes a first part and a second part that are perpendicular to each other, and a tail end of the first part of the first graphic is connected to a head end of the second part of the first graphic; orthographic projection of a first interconnection structure on the first graphic is located in the second part of the first graphic; the second graphic includes a first part and a second part that are perpendicular to each other; orthographic projection of a second interconnection structure on the second graphic is located in the second part of the second graphic; and the third graphic is located between the first graphic and the second graphic.

Abstract: A power supply housing adapted to a redundant power module includes a casing, a separation member, two front plates and a back plate. The casing includes four side plates and an installation space defined by the side plates. The separation member divides the installation space into a first sub-space and a second sub-space, and includes two first baffles located in the first sub-space and two second baffles located in the second sub-space. The two first baffles define a first installation region for disposing a redundant power module, and the two second baffles define a second installation region for disposing the redundant power module. The front plates are disposed on one end of the installation space and define a placement opening, serving as an entrance of the first and the second installation region. The back plate is disposed on one end of the installation space not provided with the front plates.