Abstract: A vertical transistor structure includes a substrate with a protruding structure, an offset layer covering a top surface of the protruding structure, a conductive layer disposed on the offset layer, and an interlayer disposed between the offset layer and the conductive layer to serve as a contact node.

Abstract: A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

Abstract: The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.

Abstract: A semiconductor structure includes a semiconductor substrate, an active area in the semiconductor substrate, two trenches intersecting the active area to thereby divide the active area into a source region and two drain regions spaced apart from the source region, a saddle-shaped N+/N?/N+ structure in the source region of the active area; and two N+ drain doping regions in the two drain regions, respectively.

Abstract: The instant disclosure relates to a semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.

Abstract: A stacked capacitor structure of the instant disclosure comprises a substrate and a plurality of stacked capacitors. The substrate has an insulating layer formed thereon and a plurality of contact plugs in the insulating layer, wherein the contact plugs are exposed on the upper surface of the insulating layer. Specially, each of the stacked capacitors comprises a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is arranged on one of the contact plugs and has a columnar base portion and a crown shaped upper portion. The dielectric layer is arranged on the lower electrode and covers the outer surface of the lower electrode. The upper electrode is arranged above the lower electrode, wherein the dielectric layer is intermediately between the upper electrode and the lower electrode.

Abstract: A dynamic random access memory unit includes a substrate having a trench disposed therein, a self-aligned trench isolation structure formed in the bottom portion of the trench, and a first trenched gate formed in the bottom portion of the trench and above the self-aligned trench isolation structure. The substrate includes at least one pillar-shaped active body having a drain region, a body region atop the drain region, and a source region atop the body region. The first trenched gate includes a first spacer formed on the side-wall in the bottom portion of the trench to selectively cover and surround the portion of the side-wall in the trench that comprises the drain region, such for defining the width of the self-aligned trench isolation structure.

Abstract: A manufacturing method of capacitor lower electrode of the instant disclosure comprises the steps of: providing a semiconductor substrate; forming a sacrificial laminate on the semiconductor substrate; forming a plurality of capacitor trenches in the sacrificial laminate; forming a plurality of lower electrode structures in the capacitor trenches respectively; etching back the sacrificial laminate to a desired thickness to expose an upper portion of each of the lower electrode structures; forming a liner layer to conformally cover the sacrificial laminate and the upper portions of the lower electrode structures; patterning the liner layer to form an insulating spacer on the sidewalls of each of the upper portions, wherein two adjacent insulating spacers are configured to have a self-aligned opening positioned therebetween; and performing a wet-etching process to remove the sacrificial laminate through the self-aligned openings.

Abstract: The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.

Abstract: A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region.

Abstract: A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source.

Abstract: The instant disclosure relates to a method for forming self-aligned isolation trenches in semiconductor substrate, comprising the following steps. The first step is providing a semiconductor substrate defined a plurality of active areas thereon. The next step is forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines. The next step is forming a self-aligned spacer on the sidewalls of each of the insulating structures. The last step is selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.

Abstract: A memory device comprises a substrate, a plurality of buried word lines, a plurality of digital contacts, a patterned insulating layer, a liner layer, a plurality of buried bit lines, and a cap layer. The buried word lines are arranged in the substrate in parallel along a first direction. Each of the digital contacts is arranged between one pair of the neighboring buried word lines. The patterned insulating layer is arranged on the buried word lines, having a plurality of contact holes opposite to the digital contacts. The liner layer is arranged on the substrate, and abuts the patterned insulating layer. The buried bit lines are arranged in parallel along a second direction different from the first direction. The cap layer arranged to cover the buried bit lines.

Abstract: A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Abstract: A semiconductor structure includes a substrate having thereon at least one conductive region; a plurality of cylinder-shaped electrodes disposed on the substrate, wherein each of the cylinder-shaped electrodes has a horizontal portion that is in direct contact with the at least one conductive region and a vertical sidewall portion connecting the horizontal portion; an upper support structure comprising a first lattice structure that is situated in a first horizontal level that is lower than a tip portion of each of the cylinder-shaped electrodes; and a lower support structure comprising a second lattice structure that interlocks middle portions of the cylinder-shaped electrodes.

Abstract: A semiconductor having through-silicon via includes a substrate, an outer dielectric liner, an inner dielectric liner and a conductive contacting layer. The substrate has a top surface and a bottom surface and defining at least one through-silicon via going through the top surface toward the bottom surface. The outer dielectric liner covers the top surface of the substrate. The inner dielectric liner covers a wall of the through-silicon via. The thickness of the inner dielectric liner reduces from the top surface toward the bottom surface. The conductive contacting liner over fills the through-silicon via and is exposed on the top surface.

Abstract: A memory device comprises a substrate, a plurality of buried word lines, a plurality of digital contacts, a patterned insulating layer, a liner layer, a plurality of buried bit lines, and a cap layer. The buried word lines are arranged in the substrate in parallel along a first direction. Each of the digital contacts is arranged between one pair of the neighboring buried word lines. The patterned insulating layer is arranged on the buried word lines, having a plurality of contact holes opposite to the digital contacts. The liner layer is arranged on the substrate, and abuts the patterned insulating layer. The buried bit lines are arranged in parallel along a second direction different from the first direction. The cap layer arranged to cover the buried bit lines.

Abstract: A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance layer. The transistor unit includes a plurality of transistors respectively disposed on the source lines. Each transistor includes a source region formed on each corresponding source line, a drain region formed above the source region, a channel region formed between the source region and the drain region, and a surrounding gate region surrounding the source region, the drain region, and the channel region. The MTJ unit includes a plurality of MTJ structures respectively disposed on the transistors. The bit line unit includes at least one bit line disposed on the MTJ unit.

Abstract: A stacked capacitor structure of the instant disclosure comprises a substrate and a plurality of stacked capacitors. The substrate has an insulating layer formed thereon and a plurality of contact plugs in the insulating layer, wherein the contact plugs are exposed on the upper surface of the insulating layer. Specially, each of the stacked capacitors comprises a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is arranged on one of the contact plugs and has a columnar base portion and a crown shaped upper portion. The dielectric layer is arranged on the lower electrode and covers the outer surface of the lower electrode. The upper electrode is arranged above the lower electrode, wherein the dielectric layer is intermediately between the upper electrode and the lower electrode.

Abstract: A method for fabricating a semiconductor memory includes the following steps. Active areas are defined in a substrate. An oxide layer is then formed on the active areas. The oxide layer is subjected to a surface treatment. A first polysilicon layer, a buffer layer and a hard mask are deposited. Recessed access devices are formed in an array region of the substrate. After the recessed access devices are formed, the hard mask and the buffer layer are removed to thereby form transistors in a peripheral region. A second polysilicon layer is deposited on the first polysilicon layer. The first and second polysilicon layers are then etched into a gate structure.