Abstract: A loading and unloading mechanism adopted for use on removable power supply modules includes in one embodiment a connection plug installed on a removable power supply and a connection trough connected to a power supply circuit of a system end (such as a personal computer). Another embodiment includes a connection trough on a system end to be installed on a holding unit which is movable to adjust the position relative to the system end according to the size of the removable power supply so that the removable power supply can be fully loaded into the computer. The loading and unloading mechanism thus formed can be adapted for the removable power supply of varying sizes and specifications.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.

Abstract: The present invention discloses a fan assembly for a power supply and improves the traditional installation of a fan onto a power supply that leaves insufficient spaces for designing the connecting holes as required by the existing installation specification, and mounts the fan into a power supply at a specific position by a specific fixing member and uses the fixing member to keep the fan at a specific interval from the end surface of the power supply without being in direct contact with the power supply. Therefore, the interval from the end surface provides sufficient space for the design of the ventilation holes for the airflow and the connecting holes as required by the installation specification of the power supply.

Abstract: A power supply having an extendable power input port connecting to a connection line to be installed on a side wall of a computer host. The side wall and the power supply form a heat dissipation passage therebetween to improve heated airflow in the computer host and increase heat dissipation effect without affecting electric plugging of the power supply.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: An anchor structure for fans mainly to fasten a fan to an installation object without damaging the fan structure includes coupling members for fastening through holes formed on the corners of the fan. Each of the coupling members includes a first fastening element running through the through hole from the rear end thereof and a second fastening element running though the front end of the through hole to engage with the first fastening element so that the coupling members are fastened securely to maintain the fan structure in an integrated manner to perform normal operation.

Abstract: An improved fixing structure for power supplies defines an accommodating area on a power supply for installing a fixing structure, and the power supply has a fixing hole on a casing of the power supply defining a limit fixing condition for the fixing structure when the power supply is pushed into the casing, and the power supply has a limit hole for installing a limit fixing member to restrict the displacement of the fixing structure, and constitutes a fixing structure that can be installed directly inside a power supply without occupying additional space, and attains the effects of fixing two fixing structures and limiting the fixing member.

Abstract: A power supply structure for high density servers bridging a system end and a power supply end includes a power receiving unit located on the system end, a power transmission unit located on the power supply end, and a conductive connection element connecting the power receiving unit and the power transmission unit through fasteners. The conductive connection element establishes electric connection with the power receiving unit and the power transmission unit through the fasteners so that power supply provided by the power supply end is transmitted from the power transmission unit to the conductive connection element which in turn transmits the power to the system end through the power receiving unit. The power supply structure of the invention may be assembled and installed quickly.

Abstract: A method of fabricating a node contact on a substrate, which contains a first conductive device and an insulating layer covering the substrate and the first conductive device, includes forming at least two conductive lines on the insulating layer, wherein the conductive lines are separated by a first distance; forming at least two second conductive devices on the insulating layer, wherein the second conductive devices are separated by a second distance, and wherein one of the conductive lines and one of the second conductive devices are separated by a third distance, and wherein both the first and second distances are greater than the third distance; forming an isolation layer of a thickness on the substrate to cover the insulating layer, the conductive lines and the second conductive devices, wherein the isolation layer comprises a dished area located between the second conductive devices; removing a portion of the isolation layer to form a spacer around the second conductive devices, and to deepen the dishe

Abstract: A multi-chip package which has a L-shaped plate and a plurality of dies arranged on the L-shaped plate. The L-shaped plate has a die package region, a plurality of solder bump pads disposed in the die package region, a plurality of pins electrically connected to a printed circuit board (PCB), and an internal circuit inside the L-shaped plate electrically connected to the plurality of solder bump pads and corresponding pins. Each die includes a plurality of bonding pads on an active surface of the die, and the bonding pads are electrically connected to corresponding solder bump pads.

Abstract: A polysilicon layer is formed on a semiconductor substrate followed by performing a collimator physical vapor deposition (PVD) process to form a titanium nitride layer on the polysilicon layer. A rapid thermal nitridation (RTN) process is then performed to tighten the structure of the titanium nitride layer. Finally, a silicide layer is formed on the barrier layer. By using the titanium nitride layer, the interface between the silicide layer and the polysilicon layer is effective prevented from occurring a spike.

Abstract: A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.

Abstract: A method of fabricating a node contact on a substrate, which contains a first conductive device and an insulating layer covering the substrate and the first conductive device, includes forming at least two conductive lines on the insulating layer, wherein the conductive lines are separated by a first distance; forming at least two second conductive devices on the insulating layer, wherein the second conductive devices are separated by a second distance, and wherein one of the conductive lines and one of the second conductive devices are separated by a third distance, and wherein both the first and second distances are greater than the third distance; forming an isolation layer of a thickness on the substrate to cover the insulating layer, the conductive lines and the second conductive devices, wherein the isolation layer comprises a dished area located between the second conductive devices; removing a portion of the isolation layer to form a spacer around the second conductive devices, and to deepen the dishe

Abstract: A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.

Abstract: A method of manufacturing a reverse electrode cylinder capacitor structure is described. A substrate having a dielectric layer and a node contact window formed thereon is provided. The dielectric layer is etched, thereby forming an opening that exposes the node contact window, and is connected to the openings formed on the two adjacent node contact windows, forming the neck-shaped structure. Next, a conductive spacer is formed on the sidewall of the opening, the conductive spacer is connected to the neck-shaped structure and forms the upper electrode of the capacitor. A dielectric layer is formed on the upper electrode, and a conductive layer is formed on the dielectric layer. A conductive layer is deposited to fill up the node contact window opening, thereby the formed conductive layer becomes the lower electrode. After performing a planarization process, the reverse electrode cylinder capacitor structure is complete.

Abstract: A method of forming a storage node of a capacitor on a silicon substrate of a semiconductor wafer is achieved. A plurality of word lines and a first dielectric layer are positioned on the silicon substrate. A plurality of node contact holes are formed within the first dielectric layer. Both a polysilicon layer and a second dielectric layer are formed respectively on the surface of the semiconductor wafer. A planarization process is performed. The top surfaces of both the polysilicon layer and the second dielectric layer in the node contact hole are aligned with the surface of the first dielectric layer. A third dielectric layer, a plurality of bit lines and a fourth dielectric layer are formed respectively on the surface of the semiconductor wafer. Sections of the fourth, the third and the second dielectric layers are etched down to the surface of the polysilicon layer to form a capacitor trench. An amorphous silicon layer is formed on the surface of the capacitor trench to produce the final storage node.